diff options
| author | Alex Smith <asmith@feralinteractive.com> | 2018-05-31 15:28:27 +0100 |
|---|---|---|
| committer | Dylan Baker <dylan@pnwbakers.com> | 2018-06-01 08:41:08 -0700 |
| commit | d6245b0a389b5efa9eff46f28a6c3ff71c075932 (patch) | |
| tree | 110e183d397e0cc360740a8e026db339c547f37f | |
| parent | 0d0135276f9b0138c5e60fb32e98d9ea3b7e64e5 (diff) | |
| download | mesa-d6245b0a389b5efa9eff46f28a6c3ff71c075932.tar.gz | |
radv: Handle GFX9 merged shaders in radv_flush_constants()
This was not previously handled correctly. For example,
push_constant_stages might only contain MESA_SHADER_VERTEX because
only that stage was changed by CmdPushConstants or
CmdBindDescriptorSets.
In that case, if vertex has been merged with tess control, then the
push constant address wouldn't be updated since
pipeline->shaders[MESA_SHADER_VERTEX] would be NULL.
Use radv_get_shader() instead of getting the shader directly so that
we get the right shader if merged. Also, skip emitting the address
redundantly - if two merged stages are set in push_constant_stages
this change would have made the address get emitted twice.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "18.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit dfff9fb6f8d4b4ecd087cc01e9841244a83558b6)
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 62d9a074ecc..1b29c4e57aa 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1577,6 +1577,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, ? cmd_buffer->state.compute_pipeline : cmd_buffer->state.pipeline; struct radv_pipeline_layout *layout = pipeline->layout; + struct radv_shader_variant *shader, *prev_shader; unsigned offset; void *ptr; uint64_t va; @@ -1601,10 +1602,16 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, MESA_SHADER_STAGES * 4); + prev_shader = NULL; radv_foreach_stage(stage, stages) { - if (pipeline->shaders[stage]) { + shader = radv_get_shader(pipeline, stage); + + /* Avoid redundantly emitting the address for merged stages. */ + if (shader && shader != prev_shader) { radv_emit_userdata_address(cmd_buffer, pipeline, stage, AC_UD_PUSH_CONSTANTS, va); + + prev_shader = shader; } } |