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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2018-05-18 20:04:12 -0700 |
|---|---|---|
| committer | Juan A. Suarez Romero <jasuarez@igalia.com> | 2018-05-23 16:28:02 +0200 |
| commit | a93a86a434b34b2e1025c3962ffd26454f787c44 (patch) | |
| tree | 0c3000031a86102918e006f48776b714889a772f | |
| parent | 6a0c2860e7237badfd71d063fa3b91a4a25f595a (diff) | |
| download | mesa-a93a86a434b34b2e1025c3962ffd26454f787c44.tar.gz | |
intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0
Fixes: d6cd14f2131a5b "i965/fs: Define new shader opcode to..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
(cherry picked from commit 417b9e5770436008a7f00cfaffe9ddf4c5a13502)
| -rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 1fb9aab51ce..b39ae880100 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -3696,6 +3696,7 @@ brw_rounding_mode(struct brw_codegen *p, if (bits != BRW_CR0_RND_MODE_MASK) { brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0), brw_imm_ud(~BRW_CR0_RND_MODE_MASK)); + brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1); /* From the Skylake PRM, Volume 7, page 760: * "Implementation Restriction on Register Access: When the control @@ -3710,6 +3711,7 @@ brw_rounding_mode(struct brw_codegen *p, if (bits) { brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0), brw_imm_ud(bits)); + brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1); brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH); } } |