diff options
| author | Anuj Phogat <anuj.phogat@gmail.com> | 2017-11-10 14:39:17 -0800 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2017-11-17 22:52:40 +0000 |
| commit | bf0c7200bd46618e6bfda3e3e0ea85afb33fa6c0 (patch) | |
| tree | cdbf59056a0abc23c666d543f4b2c6bc411e194d | |
| parent | d38e92b6e9d74b35f4b65fb5839a002d68aa04e2 (diff) | |
| download | mesa-bf0c7200bd46618e6bfda3e3e0ea85afb33fa6c0.tar.gz | |
i965: Program DWord Length in MI_FLUSH_DW
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 6165fda59b889de035b38d9a1a08ffe0da19e6a6)
Squashed with:
i965: Remove DWord length from MI_FLUSH_DW definition
Fixes: 6165fda59b8 ("i965: Program DWord Length in MI_FLUSH_DW")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 822fd2341db49cbbe813114d2d0fc1b66de4807c)
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_blit.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 4abb790612d..6bd5c54da51 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1428,7 +1428,7 @@ enum brw_pixel_shader_coverage_mask_mode { #define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23)) #define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23)) -#define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2) +#define MI_FLUSH_DW (CMD_MI | (0x26 << 23)) #define MI_STORE_REGISTER_MEM (CMD_MI | (0x24 << 23)) # define MI_STORE_REGISTER_MEM_USE_GGTT (1 << 22) diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 7e0cd1d8124..c9b2593def5 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -464,7 +464,7 @@ brw_emit_mi_flush(struct brw_context *brw) if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) { BEGIN_BATCH_BLT(4); - OUT_BATCH(MI_FLUSH_DW); + OUT_BATCH(MI_FLUSH_DW | (4 - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 819a3da2966..b766f19e289 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -106,7 +106,7 @@ set_blitter_tiling(struct brw_context *brw, assert(devinfo->gen >= 6); /* Idle the blitter before we update how tiling is interpreted. */ - OUT_BATCH(MI_FLUSH_DW); + OUT_BATCH(MI_FLUSH_DW | (4 - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); |