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author | Kenneth Graunke <kenneth@whitecape.org> | 2017-11-14 15:24:36 -0800 |
---|---|---|
committer | Emil Velikov <emil.l.velikov@gmail.com> | 2017-11-17 19:24:29 +0000 |
commit | 8ed01c0a5707e001d4fba3771f2b0e811dae232c (patch) | |
tree | fcbbfa52694a723a08a3027126a812092bb52c85 | |
parent | 957c66de1c0b48ee5959a81deeafe990edd997fa (diff) | |
download | mesa-8ed01c0a5707e001d4fba3771f2b0e811dae232c.tar.gz |
i965: Implement another VF cache invalidate workaround on Gen8+.
...and provide a better citation for the existing one.
v2:
- Apply the workaround to Gen8 too, as intended (caught by Topi).
- Restructure to add bits instead of an extra flush (based on a similar
patch by Rafael Antognolli).
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
(cherry picked from commit 8d48671492412e04c18651a779cabacf30ed0afe)
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 41 |
1 files changed, 33 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 460b8f73b6d..7e0cd1d8124 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -99,14 +99,39 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags, if (devinfo->gen == 8) gen8_add_cs_stall_workaround_bits(&flags); - if (devinfo->gen == 9 && - (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) { - /* Hardware workaround: SKL - * - * Emit Pipe Control with all bits set to zero before emitting - * a Pipe Control with VF Cache Invalidate set. - */ - brw_emit_pipe_control_flush(brw, 0); + if (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) { + if (devinfo->gen == 9) { + /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description + * lists several workarounds: + * + * "Project: SKL, KBL, BXT + * + * If the VF Cache Invalidation Enable is set to a 1 in a + * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields + * sets to 0, with the VF Cache Invalidation Enable set to 0 + * needs to be sent prior to the PIPE_CONTROL with VF Cache + * Invalidation Enable set to a 1." + */ + brw_emit_pipe_control_flush(brw, 0); + } + + if (devinfo->gen >= 8) { + /* THE PIPE_CONTROL "VF Cache Invalidation Enable" docs continue: + * + * "Project: BDW+ + * + * When VF Cache Invalidate is set “Post Sync Operation” must + * be enabled to “Write Immediate Data” or “Write PS Depth + * Count” or “Write Timestamp”." + * + * If there's a BO, we're already doing some kind of write. + * If not, add a write to the workaround BO. + */ + if (!bo) { + flags |= PIPE_CONTROL_WRITE_IMMEDIATE; + bo = brw->workaround_bo; + } + } } BEGIN_BATCH(6); |