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authorRoland Scheidegger <sroland@vmware.com>2017-11-22 03:11:33 +0100
committerEmil Velikov <emil.l.velikov@gmail.com>2017-11-29 19:45:15 +0000
commit56993f4b8a40e4fa55e97788091aaf09a8d22482 (patch)
tree90cdc4b9da8ecc57abd9b6dabb750849f1e20ab3
parent9b2c27a39e096a49e9a1ea4aeb70b688a239ef23 (diff)
downloadmesa-56993f4b8a40e4fa55e97788091aaf09a8d22482.tar.gz
r600: set DX10_CLAMP for compute shader too
I really intended to set this for all shader stages by 3835009796166968750ff46cf209f6d4208cda86 but missed it for compute shaders (because it's in a different source file...). Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit 71e630753ebbee82e8f8709da5488296b2c070c8)
-rw-r--r--src/gallium/drivers/r600/evergreen_compute.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c
index 6e87539cfe7..48c4a9ca459 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -746,8 +746,9 @@ void evergreen_emit_cs_shader(struct r600_context *rctx,
radeon_compute_set_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3);
radeon_emit(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
radeon_emit(cs, /* R_0288D4_SQ_PGM_RESOURCES_LS */
- S_0288D4_NUM_GPRS(ngpr)
- | S_0288D4_STACK_SIZE(nstack));
+ S_0288D4_NUM_GPRS(ngpr) |
+ S_0288D4_DX10_CLAMP(1) |
+ S_0288D4_STACK_SIZE(nstack));
radeon_emit(cs, 0); /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */
radeon_emit(cs, PKT3C(PKT3_NOP, 0, 0));