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| author | Matt Turner <mattst88@gmail.com> | 2017-11-08 15:14:19 -0800 |
|---|---|---|
| committer | Andres Gomez <agomez@igalia.com> | 2017-11-21 18:16:46 +0200 |
| commit | b3410696e0b700c735e06a5d4d00d6f9c1361621 (patch) | |
| tree | 9e2c1fc3f70d4301cbf51b5147543897e42877d5 | |
| parent | 70b1c115b83906987b900a5213a99991b0405da1 (diff) | |
| download | mesa-b3410696e0b700c735e06a5d4d00d6f9c1361621.tar.gz | |
i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
Fixes the following tests on CHV, BXT, and GLK:
KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115
(cherry picked from commit cfcfa0b9cd1b1d563a988b1250950057c4612ac9)
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 41f0c9a229c..1d2d734b415 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -622,8 +622,12 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) break; case nir_op_f2f64: + case nir_op_f2i64: + case nir_op_f2u64: case nir_op_i2f64: + case nir_op_i2i64: case nir_op_u2f64: + case nir_op_u2u64: /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions: * * "When source or destination is 64b (...), regioning in Align1 @@ -651,12 +655,8 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) case nir_op_f2f32: case nir_op_f2i32: case nir_op_f2u32: - case nir_op_f2i64: - case nir_op_f2u64: case nir_op_i2i32: - case nir_op_i2i64: case nir_op_u2u32: - case nir_op_u2u64: inst = bld.MOV(result, op[0]); inst->saturate = instr->dest.saturate; break; |