diff options
| author | Anuj Phogat <anuj.phogat@gmail.com> | 2017-11-09 11:30:10 -0800 |
|---|---|---|
| committer | Andres Gomez <agomez@igalia.com> | 2017-11-21 18:16:46 +0200 |
| commit | 82876e24c45f01e5209b7f8c0ab3430c54b6db28 (patch) | |
| tree | 21a4de27796e09af948470945625f596924c6486 | |
| parent | 653a203937e99fbb726b84764418599dff61952f (diff) | |
| download | mesa-82876e24c45f01e5209b7f8c0ab3430c54b6db28.tar.gz | |
i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
Number of dwords in MI_FLUSH_DW changed from 4 to 5 in gen8+.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 1dc45d75bb3ff3085f7356b8ec658111529ff76d)
[Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_pipe_control.c
src/mesa/drivers/dri/i965/intel_blit.c
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_blit.c | 14 |
2 files changed, 17 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 6a00ff587d5..0ac3dcea063 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -428,11 +428,14 @@ void brw_emit_mi_flush(struct brw_context *brw) { if (brw->batch.ring == BLT_RING && brw->gen >= 6) { - BEGIN_BATCH_BLT(4); - OUT_BATCH(MI_FLUSH_DW | (4 - 2)); + const unsigned n_dwords = brw->gen >= 8 ? 5 : 4; + BEGIN_BATCH_BLT(n_dwords); + OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); + if (n_dwords == 5) + OUT_BATCH(0); ADVANCE_BATCH(); } else { int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH; diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 6890eff3e25..2d8ea2f9e20 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -101,13 +101,16 @@ set_blitter_tiling(struct brw_context *brw, bool dst_y_tiled, bool src_y_tiled, uint32_t *__map) { + const unsigned n_dwords = brw->gen >= 8 ? 5 : 4; assert(brw->gen >= 6); /* Idle the blitter before we update how tiling is interpreted. */ - OUT_BATCH(MI_FLUSH_DW | (4 - 2)); + OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); + if (n_dwords == 5) + OUT_BATCH(0); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(BCS_SWCTRL); @@ -119,7 +122,14 @@ set_blitter_tiling(struct brw_context *brw, #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map) #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \ - BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \ + unsigned set_tiling_batch_size = 0; \ + if (dst_y_tiled || src_y_tiled) { \ + if (brw->gen >= 8) \ + set_tiling_batch_size = 16; \ + else \ + set_tiling_batch_size = 14; \ + } \ + BEGIN_BATCH_BLT(n + set_tiling_batch_size); \ if (dst_y_tiled || src_y_tiled) \ SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled) |