diff options
author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-06-06 22:49:57 +0200 |
---|---|---|
committer | Emil Velikov <emil.l.velikov@gmail.com> | 2016-06-15 09:29:13 +0100 |
commit | 28294573c737ff762b1c3f8d58bc78ddd010feca (patch) | |
tree | a004b24ca386e07681a97d692163f406909140e6 | |
parent | 7bed792ebb765d791c605313e6277b5a59402773 (diff) | |
download | mesa-28294573c737ff762b1c3f8d58bc78ddd010feca.tar.gz |
radeonsi: Reinitialize all descriptors in CE preamble.
This fixes a problem with the CE preamble and restoring only stuff in the
preamble when needed.
To illustrate suppose we have two graphics IB's 1 and 2, which are submitted in
that order. Furthermore suppose IB 1 does not use CE ram, but IB 2 does, and we
have a context switch at the start of IB 1, but not between IB 1 and IB 2.
The old code put the CE RAM loads in the preamble of IB 2. As the preamble of
IB 1 does not have the loads and the preamble of IB 2 does not get executed, the
old values are not load into CE RAM.
Fix this by always restoring the entire CE RAM.
v2: - Just load all descriptor set buffers instead of load and store the entire
CE RAM.
- Leave the ce_ram_dirty tracking in place for the non-preamble case.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Note: This commit differs from the one in master - 54f755fa0fd
("radeonsi: Reinitialize all descriptors in CE preamble.")
-rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 15 | ||||
-rw-r--r-- | src/gallium/drivers/radeonsi/si_hw_context.c | 3 | ||||
-rw-r--r-- | src/gallium/drivers/radeonsi/si_state.h | 1 |
3 files changed, 17 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 69fdb086d28..57d2ae60a6d 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -159,7 +159,7 @@ static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned s return true; } -static void si_reinitialize_ce_ram(struct si_context *sctx, +static void si_ce_reinitialize_descriptors(struct si_context *sctx, struct si_descriptors *desc) { if (desc->buffer) { @@ -185,6 +185,17 @@ static void si_reinitialize_ce_ram(struct si_context *sctx, desc->ce_ram_dirty = false; } +void si_ce_reinitialize_all_descriptors(struct si_context *sctx) +{ + for (int i = 0; i < SI_NUM_SHADERS; i++) { + si_ce_reinitialize_descriptors(sctx, &sctx->const_buffers[i].desc); + si_ce_reinitialize_descriptors(sctx, &sctx->shader_buffers[i].desc); + si_ce_reinitialize_descriptors(sctx, &sctx->samplers[i].views.desc); + si_ce_reinitialize_descriptors(sctx, &sctx->images[i].desc); + } + si_ce_reinitialize_descriptors(sctx, &sctx->rw_buffers.desc); +} + void si_ce_enable_loads(struct radeon_winsys_cs *ib) { radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); @@ -206,7 +217,7 @@ static bool si_upload_descriptors(struct si_context *sctx, uint32_t const* list = (uint32_t const*)desc->list; if (desc->ce_ram_dirty) - si_reinitialize_ce_ram(sctx, desc); + si_ce_reinitialize_descriptors(sctx, desc); while(desc->dirty_mask) { int begin, count; diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index dcf206df216..1a887c1a4e4 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -207,6 +207,9 @@ void si_begin_new_cs(struct si_context *ctx) else if (ctx->ce_ib) si_ce_enable_loads(ctx->ce_ib); + if (ctx->ce_preamble_ib) + si_ce_reinitialize_all_descriptors(ctx); + ctx->framebuffer.dirty_cbufs = (1 << 8) - 1; ctx->framebuffer.dirty_zsbuf = true; si_mark_atom_dirty(ctx, &ctx->framebuffer.atom); diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index a3589d4611d..aea98ae464f 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -250,6 +250,7 @@ struct si_buffer_resources { } while(0) /* si_descriptors.c */ +void si_ce_reinitialize_all_descriptors(struct si_context *sctx); void si_ce_enable_loads(struct radeon_winsys_cs *ib); void si_set_ring_buffer(struct pipe_context *ctx, uint slot, struct pipe_resource *buffer, |