diff options
| author | Rob Clark <robdclark@chromium.org> | 2019-12-03 13:44:35 -0800 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2019-12-04 13:08:52 -0800 |
| commit | 937b9055698be0dfdb7d2e0673a989e2ecc05912 (patch) | |
| tree | 03c22d0d152a5c63f301e62314615649a25b75dc | |
| parent | 4e47c205b9749aebb258075da36d176e1d453eb4 (diff) | |
| download | mesa-937b9055698be0dfdb7d2e0673a989e2ecc05912.tar.gz | |
freedreno/ir3: fix neverball assert in case of unused VS inputs
The logic to ensure VS and BS inputs are aligned wasn't accounting for
unused inputs in VS. This *usually* doesn't happen, but it seems it
can in the case of ARB programs?
Fixes assert:
```
fd6_program_create: Assertion `bs->inputs[i].regid == vs->inputs[i].regid' failed.
```
Fixes: 882d53d8e36 ("freedreno/ir3+a6xx: same VBO state for draw/binning")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
| -rw-r--r-- | src/freedreno/ir3/ir3.h | 4 | ||||
| -rw-r--r-- | src/freedreno/ir3/ir3_compiler_nir.c | 19 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a6xx/fd6_program.c | 3 |
3 files changed, 19 insertions, 7 deletions
diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h index afff38b9b60..aa89e765bef 100644 --- a/src/freedreno/ir3/ir3.h +++ b/src/freedreno/ir3/ir3.h @@ -614,6 +614,10 @@ static inline uint32_t reg_comp(struct ir3_register *reg) return reg->num & 0x3; } +#define INVALID_REG regid(63, 0) +#define VALIDREG(r) ((r) != INVALID_REG) +#define CONDREG(r, val) COND(VALIDREG(r), (val)) + static inline bool is_flow(struct ir3_instruction *instr) { return (opc_cat(instr->opc) == 0); diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 271e86522f5..1d888f42446 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -3472,9 +3472,9 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, */ for (unsigned i = 0; i < so->inputs_count; i++) - so->inputs[i].regid = regid(63, 0); + so->inputs[i].regid = INVALID_REG; for (unsigned i = 0; i < so->outputs_count; i++) - so->outputs[i].regid = regid(63, 0); + so->outputs[i].regid = INVALID_REG; struct ir3_instruction *out; foreach_output(out, ir) { @@ -3490,8 +3490,19 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, assert(in->opc == OPC_META_INPUT); unsigned inidx = in->input.inidx; - so->inputs[inidx].regid = in->regs[0]->num; - so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF); + if (pre_assign_inputs) { + if (VALIDREG(so->nonbinning->inputs[inidx].regid)) { + compile_assert(ctx, in->regs[0]->num == + so->nonbinning->inputs[inidx].regid); + compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) == + so->nonbinning->inputs[inidx].half); + } + so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid; + so->inputs[inidx].half = so->nonbinning->inputs[inidx].half; + } else { + so->inputs[inidx].regid = in->regs[0]->num; + so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF); + } } if (ctx->astc_srgb) diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c index a37d1431d6c..888a4b91d90 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c @@ -256,9 +256,6 @@ setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *stat OUT_RING(ring, state->fs->image_mapping.num_ibo); } -#define VALIDREG(r) ((r) != regid(63,0)) -#define CONDREG(r, val) COND(VALIDREG(r), (val)) - static inline uint32_t next_regid(uint32_t reg, uint32_t increment) { |