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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2014-12-23 13:59:16 -0800 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-02-07 08:08:59 -0800 |
| commit | 7ea1e3749738c63388d3bcca327e4e4dd28f17b8 (patch) | |
| tree | 0647f15a5b8743ad73e812769f8f64f4339b37dc | |
| parent | efde74c89dd8596b4cc0dfd9601e55832833f20e (diff) | |
| download | mesa-7ea1e3749738c63388d3bcca327e4e4dd28f17b8.tar.gz | |
i965: Add more stringent blitter assertions
Blits to or from a y-tiled surface must always be a multiple of the tile size.
From page 16 of the HSW PRM
(https://01.org/linuxgraphics/sites/default/files/documentation/intel-gfx-prm-osrc-hsw-memory-views.pdf#16)
"The pitch of a tiled enclosing region must be an integral number of tile
widths"
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_blit.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index e919528894a..9500bd70e81 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -307,6 +307,9 @@ intelEmitCopyBlit(struct brw_context *brw, if ((dst_y_tiled || src_y_tiled) && brw->gen < 6) return false; + assert(!dst_y_tiled || (dst_pitch % 128) == 0); + assert(!src_y_tiled || (src_pitch % 128) == 0); + /* do space check before going any further */ do { aper_array[0] = brw->batch.bo; |