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| author | Vicențiu Ciorbaru <vicentiu@mariadb.org> | 2016-08-18 14:00:40 +0300 |
|---|---|---|
| committer | Vicențiu Ciorbaru <vicentiu@mariadb.org> | 2016-08-18 14:08:14 +0300 |
| commit | 9fbcff274ab059c2397a93c38c4ed41a6abd8ff3 (patch) | |
| tree | d8ae236007f4d9964ee40ec19a00fa07473d4449 | |
| parent | fab08402800f67aebed6eef0132141cd6fed9df0 (diff) | |
| download | mariadb-git-bb-10.0-mdev-10341.tar.gz | |
MDEV-10341: InnoDB: Failing assertion: mutex_own(mutex) - mutex_exit_funcbb-10.0-mdev-10341
Followup from 5.5 patch. Removing memory barriers on intel is wrong as
this doesn't prevent the compiler and/or processor from reorganizing reads
before the mutex release. Forcing a memory barrier before reading the waiters will
guarantee that no speculative reading takes place.
| -rw-r--r-- | storage/innobase/include/os0sync.h | 10 | ||||
| -rw-r--r-- | storage/xtradb/include/os0sync.h | 10 |
2 files changed, 2 insertions, 18 deletions
diff --git a/storage/innobase/include/os0sync.h b/storage/innobase/include/os0sync.h index bd9acb13028..0754210c47a 100644 --- a/storage/innobase/include/os0sync.h +++ b/storage/innobase/include/os0sync.h @@ -849,15 +849,7 @@ for synchronization */ } while (0); /** barrier definitions for memory ordering */ -#ifdef IB_STRONG_MEMORY_MODEL -/* Performance regression was observed at some conditions for Intel -architecture. Disable memory barrier for Intel architecture for now. */ -# define os_rmb do { } while(0) -# define os_wmb do { } while(0) -# define os_mb do { } while(0) -# define IB_MEMORY_BARRIER_STARTUP_MSG \ - "Memory barrier is not used" -#elif defined(HAVE_IB_GCC_ATOMIC_THREAD_FENCE) +#if defined(HAVE_IB_GCC_ATOMIC_THREAD_FENCE) # define HAVE_MEMORY_BARRIER # define os_rmb __atomic_thread_fence(__ATOMIC_ACQUIRE) # define os_wmb __atomic_thread_fence(__ATOMIC_RELEASE) diff --git a/storage/xtradb/include/os0sync.h b/storage/xtradb/include/os0sync.h index c7a9318c841..f6207555f1a 100644 --- a/storage/xtradb/include/os0sync.h +++ b/storage/xtradb/include/os0sync.h @@ -900,15 +900,7 @@ for synchronization */ } while (0); /** barrier definitions for memory ordering */ -#ifdef IB_STRONG_MEMORY_MODEL -/* Performance regression was observed at some conditions for Intel -architecture. Disable memory barrier for Intel architecture for now. */ -# define os_rmb do { } while(0) -# define os_wmb do { } while(0) -# define os_mb do { } while(0) -# define IB_MEMORY_BARRIER_STARTUP_MSG \ - "Memory barrier is not used" -#elif defined(HAVE_IB_GCC_ATOMIC_THREAD_FENCE) +#if defined(HAVE_IB_GCC_ATOMIC_THREAD_FENCE) # define HAVE_MEMORY_BARRIER # define os_rmb __atomic_thread_fence(__ATOMIC_ACQUIRE) # define os_wmb __atomic_thread_fence(__ATOMIC_RELEASE) |