1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
declare i64 @llvm.riscv.vsetvli(
i64, i64, i64);
define signext i32 @vsetvl_sext() {
; CHECK-LABEL: vsetvl_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 1, e16, m2, ta, ma
; CHECK-NEXT: ret
%a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1)
%b = trunc i64 %a to i32
ret i32 %b
}
define zeroext i32 @vsetvl_zext() {
; CHECK-LABEL: vsetvl_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 1, e16, m2, ta, ma
; CHECK-NEXT: ret
%a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1)
%b = trunc i64 %a to i32
ret i32 %b
}
define i64 @vsetvl_and17bits() {
; CHECK-LABEL: vsetvl_and17bits:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 1, e16, m2, ta, ma
; CHECK-NEXT: ret
%a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1)
%b = and i64 %a, 131071
ret i64 %b
}
|
