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-rw-r--r--test/MC/AArch64/SVE/assembler_tests/add.s66
-rw-r--r--test/MC/AArch64/SVE/assembler_tests/sub.s66
-rw-r--r--test/MC/AArch64/SVE/disassembler_tests/add.s50
-rw-r--r--test/MC/AArch64/SVE/disassembler_tests/sub.s50
-rw-r--r--test/MC/Disassembler/Mips/micromips32r3/valid-el.txt1
-rw-r--r--test/MC/Disassembler/Mips/micromips32r3/valid.txt1
-rw-r--r--test/MC/Disassembler/Mips/micromips32r6/valid.txt2
-rw-r--r--test/MC/Disassembler/Mips/micromips64r6/valid.txt2
-rw-r--r--test/MC/Disassembler/X86/prefixes-i386.txt78
-rw-r--r--test/MC/Disassembler/X86/prefixes-x86_64.txt24
-rw-r--r--test/MC/Disassembler/X86/prefixes.txt66
-rw-r--r--test/MC/Disassembler/X86/simple-tests.txt9
-rw-r--r--test/MC/Mips/micromips32r6/valid.s2
-rw-r--r--test/MC/Mips/micromips64r6/valid.s2
-rw-r--r--test/MC/Mips/tls-symbols.s28
15 files changed, 325 insertions, 122 deletions
diff --git a/test/MC/AArch64/SVE/assembler_tests/add.s b/test/MC/AArch64/SVE/assembler_tests/add.s
new file mode 100644
index 000000000000..7906dbbaf88c
--- /dev/null
+++ b/test/MC/AArch64/SVE/assembler_tests/add.s
@@ -0,0 +1,66 @@
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve < %s | FileCheck %s
+// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=-sve 2>&1 < %s | FileCheck --check-prefix=CHECK-ERROR %s
+add z31.s, z31.s, z31.s // 00000100-10111111-00000011-11111111
+// CHECK: add z31.s, z31.s, z31.s // encoding: [0xff,0x03,0xbf,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-10111111-00000011-11111111
+add z23.d, z13.d, z8.d // 00000100-11101000-00000001-10110111
+// CHECK: add z23.d, z13.d, z8.d // encoding: [0xb7,0x01,0xe8,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-11101000-00000001-10110111
+add z0.s, z0.s, z0.s // 00000100-10100000-00000000-00000000
+// CHECK: add z0.s, z0.s, z0.s // encoding: [0x00,0x00,0xa0,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-10100000-00000000-00000000
+add z31.d, z31.d, z31.d // 00000100-11111111-00000011-11111111
+// CHECK: add z31.d, z31.d, z31.d // encoding: [0xff,0x03,0xff,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-11111111-00000011-11111111
+add z21.b, z10.b, z21.b // 00000100-00110101-00000001-01010101
+// CHECK: add z21.b, z10.b, z21.b // encoding: [0x55,0x01,0x35,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-00110101-00000001-01010101
+add z31.b, z31.b, z31.b // 00000100-00111111-00000011-11111111
+// CHECK: add z31.b, z31.b, z31.b // encoding: [0xff,0x03,0x3f,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-00111111-00000011-11111111
+add z0.h, z0.h, z0.h // 00000100-01100000-00000000-00000000
+// CHECK: add z0.h, z0.h, z0.h // encoding: [0x00,0x00,0x60,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-01100000-00000000-00000000
+add z23.b, z13.b, z8.b // 00000100-00101000-00000001-10110111
+// CHECK: add z23.b, z13.b, z8.b // encoding: [0xb7,0x01,0x28,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-00101000-00000001-10110111
+add z0.d, z0.d, z0.d // 00000100-11100000-00000000-00000000
+// CHECK: add z0.d, z0.d, z0.d // encoding: [0x00,0x00,0xe0,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-11100000-00000000-00000000
+add z31.h, z31.h, z31.h // 00000100-01111111-00000011-11111111
+// CHECK: add z31.h, z31.h, z31.h // encoding: [0xff,0x03,0x7f,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-01111111-00000011-11111111
+add z0.b, z0.b, z0.b // 00000100-00100000-00000000-00000000
+// CHECK: add z0.b, z0.b, z0.b // encoding: [0x00,0x00,0x20,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-00100000-00000000-00000000
+add z21.d, z10.d, z21.d // 00000100-11110101-00000001-01010101
+// CHECK: add z21.d, z10.d, z21.d // encoding: [0x55,0x01,0xf5,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-11110101-00000001-01010101
+add z21.h, z10.h, z21.h // 00000100-01110101-00000001-01010101
+// CHECK: add z21.h, z10.h, z21.h // encoding: [0x55,0x01,0x75,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-01110101-00000001-01010101
+add z21.s, z10.s, z21.s // 00000100-10110101-00000001-01010101
+// CHECK: add z21.s, z10.s, z21.s // encoding: [0x55,0x01,0xb5,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-10110101-00000001-01010101
+add z23.h, z13.h, z8.h // 00000100-01101000-00000001-10110111
+// CHECK: add z23.h, z13.h, z8.h // encoding: [0xb7,0x01,0x68,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-01101000-00000001-10110111
+add z23.s, z13.s, z8.s // 00000100-10101000-00000001-10110111
+// CHECK: add z23.s, z13.s, z8.s // encoding: [0xb7,0x01,0xa8,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-10101000-00000001-10110111
diff --git a/test/MC/AArch64/SVE/assembler_tests/sub.s b/test/MC/AArch64/SVE/assembler_tests/sub.s
new file mode 100644
index 000000000000..ee283afdb7fc
--- /dev/null
+++ b/test/MC/AArch64/SVE/assembler_tests/sub.s
@@ -0,0 +1,66 @@
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve < %s | FileCheck %s
+// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=-sve 2>&1 < %s | FileCheck --check-prefix=CHECK-ERROR %s
+sub z0.h, z0.h, z0.h // 00000100-01100000-00000100-00000000
+// CHECK: sub z0.h, z0.h, z0.h // encoding: [0x00,0x04,0x60,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-01100000-00000100-00000000
+sub z21.b, z10.b, z21.b // 00000100-00110101-00000101-01010101
+// CHECK: sub z21.b, z10.b, z21.b // encoding: [0x55,0x05,0x35,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-00110101-00000101-01010101
+sub z31.h, z31.h, z31.h // 00000100-01111111-00000111-11111111
+// CHECK: sub z31.h, z31.h, z31.h // encoding: [0xff,0x07,0x7f,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-01111111-00000111-11111111
+sub z21.h, z10.h, z21.h // 00000100-01110101-00000101-01010101
+// CHECK: sub z21.h, z10.h, z21.h // encoding: [0x55,0x05,0x75,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-01110101-00000101-01010101
+sub z31.b, z31.b, z31.b // 00000100-00111111-00000111-11111111
+// CHECK: sub z31.b, z31.b, z31.b // encoding: [0xff,0x07,0x3f,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-00111111-00000111-11111111
+sub z0.s, z0.s, z0.s // 00000100-10100000-00000100-00000000
+// CHECK: sub z0.s, z0.s, z0.s // encoding: [0x00,0x04,0xa0,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-10100000-00000100-00000000
+sub z23.b, z13.b, z8.b // 00000100-00101000-00000101-10110111
+// CHECK: sub z23.b, z13.b, z8.b // encoding: [0xb7,0x05,0x28,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-00101000-00000101-10110111
+sub z21.d, z10.d, z21.d // 00000100-11110101-00000101-01010101
+// CHECK: sub z21.d, z10.d, z21.d // encoding: [0x55,0x05,0xf5,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-11110101-00000101-01010101
+sub z21.s, z10.s, z21.s // 00000100-10110101-00000101-01010101
+// CHECK: sub z21.s, z10.s, z21.s // encoding: [0x55,0x05,0xb5,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-10110101-00000101-01010101
+sub z0.b, z0.b, z0.b // 00000100-00100000-00000100-00000000
+// CHECK: sub z0.b, z0.b, z0.b // encoding: [0x00,0x04,0x20,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-00100000-00000100-00000000
+sub z23.d, z13.d, z8.d // 00000100-11101000-00000101-10110111
+// CHECK: sub z23.d, z13.d, z8.d // encoding: [0xb7,0x05,0xe8,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-11101000-00000101-10110111
+sub z23.s, z13.s, z8.s // 00000100-10101000-00000101-10110111
+// CHECK: sub z23.s, z13.s, z8.s // encoding: [0xb7,0x05,0xa8,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-10101000-00000101-10110111
+sub z31.d, z31.d, z31.d // 00000100-11111111-00000111-11111111
+// CHECK: sub z31.d, z31.d, z31.d // encoding: [0xff,0x07,0xff,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-11111111-00000111-11111111
+sub z23.h, z13.h, z8.h // 00000100-01101000-00000101-10110111
+// CHECK: sub z23.h, z13.h, z8.h // encoding: [0xb7,0x05,0x68,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-01101000-00000101-10110111
+sub z0.d, z0.d, z0.d // 00000100-11100000-00000100-00000000
+// CHECK: sub z0.d, z0.d, z0.d // encoding: [0x00,0x04,0xe0,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-11100000-00000100-00000000
+sub z31.s, z31.s, z31.s // 00000100-10111111-00000111-11111111
+// CHECK: sub z31.s, z31.s, z31.s // encoding: [0xff,0x07,0xbf,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR-NEXT: 00000100-10111111-00000111-11111111
diff --git a/test/MC/AArch64/SVE/disassembler_tests/add.s b/test/MC/AArch64/SVE/disassembler_tests/add.s
new file mode 100644
index 000000000000..22a61fb4a844
--- /dev/null
+++ b/test/MC/AArch64/SVE/disassembler_tests/add.s
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -disassemble -mattr=+sve < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -disassemble -mattr=-sve 2>&1 < %s | FileCheck --check-prefix=CHECK-ERROR %s
+0xff,0x03,0xbf,0x04
+# CHECK: add z31.s, z31.s, z31.s // encoding: [0xff,0x03,0xbf,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xb7,0x01,0xe8,0x04
+# CHECK: add z23.d, z13.d, z8.d // encoding: [0xb7,0x01,0xe8,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x00,0x00,0xa0,0x04
+# CHECK: add z0.s, z0.s, z0.s // encoding: [0x00,0x00,0xa0,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xff,0x03,0xff,0x04
+# CHECK: add z31.d, z31.d, z31.d // encoding: [0xff,0x03,0xff,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x55,0x01,0x35,0x04
+# CHECK: add z21.b, z10.b, z21.b // encoding: [0x55,0x01,0x35,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xff,0x03,0x3f,0x04
+# CHECK: add z31.b, z31.b, z31.b // encoding: [0xff,0x03,0x3f,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x00,0x00,0x60,0x04
+# CHECK: add z0.h, z0.h, z0.h // encoding: [0x00,0x00,0x60,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xb7,0x01,0x28,0x04
+# CHECK: add z23.b, z13.b, z8.b // encoding: [0xb7,0x01,0x28,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x00,0x00,0xe0,0x04
+# CHECK: add z0.d, z0.d, z0.d // encoding: [0x00,0x00,0xe0,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xff,0x03,0x7f,0x04
+# CHECK: add z31.h, z31.h, z31.h // encoding: [0xff,0x03,0x7f,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x00,0x00,0x20,0x04
+# CHECK: add z0.b, z0.b, z0.b // encoding: [0x00,0x00,0x20,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x55,0x01,0xf5,0x04
+# CHECK: add z21.d, z10.d, z21.d // encoding: [0x55,0x01,0xf5,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x55,0x01,0x75,0x04
+# CHECK: add z21.h, z10.h, z21.h // encoding: [0x55,0x01,0x75,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x55,0x01,0xb5,0x04
+# CHECK: add z21.s, z10.s, z21.s // encoding: [0x55,0x01,0xb5,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xb7,0x01,0x68,0x04
+# CHECK: add z23.h, z13.h, z8.h // encoding: [0xb7,0x01,0x68,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xb7,0x01,0xa8,0x04
+# CHECK: add z23.s, z13.s, z8.s // encoding: [0xb7,0x01,0xa8,0x04]
+# CHECK-ERROR: invalid instruction encoding
diff --git a/test/MC/AArch64/SVE/disassembler_tests/sub.s b/test/MC/AArch64/SVE/disassembler_tests/sub.s
new file mode 100644
index 000000000000..e7acde952a78
--- /dev/null
+++ b/test/MC/AArch64/SVE/disassembler_tests/sub.s
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -disassemble -mattr=+sve < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -disassemble -mattr=-sve 2>&1 < %s | FileCheck --check-prefix=CHECK-ERROR %s
+0x00,0x04,0x60,0x04
+# CHECK: sub z0.h, z0.h, z0.h // encoding: [0x00,0x04,0x60,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x55,0x05,0x35,0x04
+# CHECK: sub z21.b, z10.b, z21.b // encoding: [0x55,0x05,0x35,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xff,0x07,0x7f,0x04
+# CHECK: sub z31.h, z31.h, z31.h // encoding: [0xff,0x07,0x7f,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x55,0x05,0x75,0x04
+# CHECK: sub z21.h, z10.h, z21.h // encoding: [0x55,0x05,0x75,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xff,0x07,0x3f,0x04
+# CHECK: sub z31.b, z31.b, z31.b // encoding: [0xff,0x07,0x3f,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x00,0x04,0xa0,0x04
+# CHECK: sub z0.s, z0.s, z0.s // encoding: [0x00,0x04,0xa0,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xb7,0x05,0x28,0x04
+# CHECK: sub z23.b, z13.b, z8.b // encoding: [0xb7,0x05,0x28,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x55,0x05,0xf5,0x04
+# CHECK: sub z21.d, z10.d, z21.d // encoding: [0x55,0x05,0xf5,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x55,0x05,0xb5,0x04
+# CHECK: sub z21.s, z10.s, z21.s // encoding: [0x55,0x05,0xb5,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x00,0x04,0x20,0x04
+# CHECK: sub z0.b, z0.b, z0.b // encoding: [0x00,0x04,0x20,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xb7,0x05,0xe8,0x04
+# CHECK: sub z23.d, z13.d, z8.d // encoding: [0xb7,0x05,0xe8,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xb7,0x05,0xa8,0x04
+# CHECK: sub z23.s, z13.s, z8.s // encoding: [0xb7,0x05,0xa8,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xff,0x07,0xff,0x04
+# CHECK: sub z31.d, z31.d, z31.d // encoding: [0xff,0x07,0xff,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xb7,0x05,0x68,0x04
+# CHECK: sub z23.h, z13.h, z8.h // encoding: [0xb7,0x05,0x68,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0x00,0x04,0xe0,0x04
+# CHECK: sub z0.d, z0.d, z0.d // encoding: [0x00,0x04,0xe0,0x04]
+# CHECK-ERROR: invalid instruction encoding
+0xff,0x07,0xbf,0x04
+# CHECK: sub z31.s, z31.s, z31.s // encoding: [0xff,0x07,0xbf,0x04]
+# CHECK-ERROR: invalid instruction encoding
diff --git a/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt b/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
index dc76f48a95a5..0cd74f5ba71c 100644
--- a/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
+++ b/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
@@ -27,6 +27,7 @@
0x09 0x46 # CHECK: mfhi $9
0x49 0x46 # CHECK: mflo $9
0x21 0x0f # CHECK: move $25, $1
+0x9a 0x85 # CHECK: movep $4, $21, $18, $17
0xa9 0x45 # CHECK: jrc $9
0xc9 0x45 # CHECK: jalr $9
0xe9 0x45 # CHECK: jalrs16 $9
diff --git a/test/MC/Disassembler/Mips/micromips32r3/valid.txt b/test/MC/Disassembler/Mips/micromips32r3/valid.txt
index 38d6897e1c4f..dbab070b874e 100644
--- a/test/MC/Disassembler/Mips/micromips32r3/valid.txt
+++ b/test/MC/Disassembler/Mips/micromips32r3/valid.txt
@@ -27,6 +27,7 @@
0x46 0x09 # CHECK: mfhi $9
0x46 0x49 # CHECK: mflo $9
0x0f 0x21 # CHECK: move $25, $1
+0x85 0x9a # CHECK: movep $4, $21, $18, $17
0x45 0xa9 # CHECK: jrc $9
0x45 0xc9 # CHECK: jalr $9
0x45 0xe9 # CHECK: jalrs16 $9
diff --git a/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/test/MC/Disassembler/Mips/micromips32r6/valid.txt
index f32f2532c24c..462866d33475 100644
--- a/test/MC/Disassembler/Mips/micromips32r6/valid.txt
+++ b/test/MC/Disassembler/Mips/micromips32r6/valid.txt
@@ -21,7 +21,7 @@
0x29 0x82 # CHECK: lhu16 $3, 4($16)
0x09 0x94 # CHECK: lbu16 $3, 4($17)
0x09 0x9f # CHECK: lbu16 $3, -1($17)
-0x84 0x34 # CHECK: movep $5, $6, $2, $3
+0x44 0x36 # CHECK: movep $5, $6, $2, $3
0x04 0xcc # CHECK: addu16 $6, $17, $4
0x44 0x21 # CHECK: and16 $16, $2
0x2e 0x56 # CHECK: andi16 $4, $5, 8
diff --git a/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/test/MC/Disassembler/Mips/micromips64r6/valid.txt
index 9186e66d4d0b..07cea0d77c5a 100644
--- a/test/MC/Disassembler/Mips/micromips64r6/valid.txt
+++ b/test/MC/Disassembler/Mips/micromips64r6/valid.txt
@@ -23,7 +23,7 @@
0x45 0x2b # CHECK: jalr $9
0x45 0x23 # CHECK: jrc16 $9
0x44 0xb3 # CHECK: jrcaddiusp 20
-0x84 0x34 # CHECK: movep $5, $6, $2, $3
+0x44 0x36 # CHECK: movep $5, $6, $2, $3
0x45 0xf9 # CHECK: or16 $3, $7
0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
diff --git a/test/MC/Disassembler/X86/prefixes-i386.txt b/test/MC/Disassembler/X86/prefixes-i386.txt
index ff2fb2238737..3152cc31aad1 100644
--- a/test/MC/Disassembler/X86/prefixes-i386.txt
+++ b/test/MC/Disassembler/X86/prefixes-i386.txt
@@ -3,85 +3,59 @@
# CHECK: movl %fs:24, %eax
0x64 0xa1 0x18 0x00 0x00 0x00 # mov eax, dword ptr fs:[18h]
-# CHECK: rep
-# CHECK-NEXT: insb %dx, %es:(%edi)
+# CHECK: rep insb %dx, %es:(%edi)
0xf3 0x6c #rep ins
-# CHECK: rep
-# CHECK-NEXT: insl %dx, %es:(%edi)
+# CHECK: rep insl %dx, %es:(%edi)
0xf3 0x6d #rep ins
-# CHECK: rep
-# CHECK-NEXT: movsb (%esi), %es:(%edi)
+# CHECK: rep movsb (%esi), %es:(%edi)
0xf3 0xa4 #rep movs
-# CHECK: rep
-# CHECK-NEXT: movsl (%esi), %es:(%edi)
+# CHECK: rep movsl (%esi), %es:(%edi)
0xf3 0xa5 #rep movs
-# CHECK: rep
-# CHECK-NEXT: outsb (%esi), %dx
+# CHECK: rep outsb (%esi), %dx
0xf3 0x6e #rep outs
-# CHECK: rep
-# CHECK-NEXT: outsl (%esi), %dx
+# CHECK: rep outsl (%esi), %dx
0xf3 0x6f #rep outs
-# CHECK: rep
-# CHECK-NEXT: lodsb (%esi), %al
+# CHECK: rep lodsb (%esi), %al
0xf3 0xac #rep lods
-# CHECK: rep
-# CHECK-NEXT: lodsl (%esi), %eax
+# CHECK: rep lodsl (%esi), %eax
0xf3 0xad #rep lods
-# CHECK: rep
-# CHECK-NEXT: stosb %al, %es:(%edi)
+# CHECK: rep stosb %al, %es:(%edi)
0xf3 0xaa #rep stos
-# CHECK: rep
-# CHECK-NEXT: stosl %eax, %es:(%edi)
+# CHECK: rep stosl %eax, %es:(%edi)
0xf3 0xab #rep stos
-# CHECK: rep
-# CHECK-NEXT: cmpsb %es:(%edi), (%esi)
+# CHECK: rep cmpsb %es:(%edi), (%esi)
0xf3 0xa6 #rep cmps
-# CHECK: rep
-# CHECK-NEXT: cmpsl %es:(%edi), (%esi)
+# CHECK: rep cmpsl %es:(%edi), (%esi)
0xf3 0xa7 #repe cmps
-# CHECK: rep
-# CHECK-NEXT: scasb %es:(%edi), %al
+# CHECK: rep scasb %es:(%edi), %al
0xf3 0xae #repe scas
-# CHECK: rep
-# CHECK-NEXT: scasl %es:(%edi), %eax
+# CHECK: rep scasl %es:(%edi), %eax
0xf3 0xaf #repe scas
-# CHECK: repne
-# CHECK-NEXT: cmpsb %es:(%edi), (%esi)
+# CHECK: repne cmpsb %es:(%edi), (%esi)
0xf2 0xa6 #repne cmps
-# CHECK: repne
-# CHECK-NEXT: cmpsl %es:(%edi), (%esi)
+# CHECK: repne cmpsl %es:(%edi), (%esi)
0xf2 0xa7 #repne cmps
-# CHECK: repne
-# CHECK-NEXT: scasb %es:(%edi), %al
+# CHECK: repne scasb %es:(%edi), %al
0xf2 0xae #repne scas
-# CHECK: repne
-# CHECK-NEXT: scasl %es:(%edi), %eax
+# CHECK: repne scasl %es:(%edi), %eax
0xf2 0xaf #repne scas
-# CHECK: repne
-# CHECK-NEXT: scasw %es:(%edi), %ax
+# CHECK: repne scasw %es:(%edi), %ax
0xf2 0x66 0xaf
-# CHECK: repne
-# CHECK-NEXT: scasw %es:(%edi), %ax
+# CHECK: repne scasw %es:(%edi), %ax
0x66 0xf2 0xaf
-# CHECK: rep
-# CHECK-NEXT: scasw %es:(%edi), %ax
+# CHECK: rep scasw %es:(%edi), %ax
0xf3 0x66 0xaf
-# CHECK: rep
-# CHECK-NEXT: scasw %es:(%edi), %ax
+# CHECK: rep scasw %es:(%edi), %ax
0x66 0xf3 0xaf
-# CHECK: repne
-# CHECK: insw %dx, %es:(%edi)
+# CHECK: repne insw %dx, %es:(%edi)
0xf2 0x66 0x6d
-# CHECK: repne
-# CHECK: insw %dx, %es:(%edi)
+# CHECK: repne insw %dx, %es:(%edi)
0x66 0xf2 0x6d
-# CHECK: rep
-# CHECK: insw %dx, %es:(%edi)
+# CHECK: rep insw %dx, %es:(%edi)
0xf3 0x66 0x6d
-# CHECK: rep
-# CHECK: insw %dx, %es:(%edi)
+# CHECK: rep insw %dx, %es:(%edi)
0x66 0xf3 0x6d
diff --git a/test/MC/Disassembler/X86/prefixes-x86_64.txt b/test/MC/Disassembler/X86/prefixes-x86_64.txt
index 7a9208f7b639..c9bf512aa758 100644
--- a/test/MC/Disassembler/X86/prefixes-x86_64.txt
+++ b/test/MC/Disassembler/X86/prefixes-x86_64.txt
@@ -9,30 +9,22 @@
# CHECK: mulsd %xmm7, %xmm7
0xf2 0x66 0x0f 0x59 0xff
-# CHECK: repne
-# CHECK-NEXT: scasw %es:(%rdi), %ax
+# CHECK: repne scasw %es:(%rdi), %ax
0xf2 0x66 0xaf
-# CHECK: rep
-# CHECK-NEXT: scasw %es:(%rdi), %ax
+# CHECK: repne scasw %es:(%rdi), %ax
0x66 0xf2 0xaf
-# CHECK: rep
-# CHECK-NEXT: scasw %es:(%rdi), %ax
+# CHECK: rep scasw %es:(%rdi), %ax
0xf3 0x66 0xaf
-# CHECK: rep
-# CHECK-NEXT: scasw %es:(%rdi), %ax
+# CHECK: rep scasw %es:(%rdi), %ax
0x66 0xf3 0xaf
-# CHECK: repne
-# CHECK: insw %dx, %es:(%rdi)
+# CHECK: repne insw %dx, %es:(%rdi)
0xf2 0x66 0x6d
-# CHECK: repne
-# CHECK: insw %dx, %es:(%rdi)
+# CHECK: repne insw %dx, %es:(%rdi)
0x66 0xf2 0x6d
-# CHECK: rep
-# CHECK: insw %dx, %es:(%rdi)
+# CHECK: rep insw %dx, %es:(%rdi)
0xf3 0x66 0x6d
-# CHECK: rep
-# CHECK: insw %dx, %es:(%rdi)
+# CHECK: rep insw %dx, %es:(%rdi)
0x66 0xf3 0x6d
diff --git a/test/MC/Disassembler/X86/prefixes.txt b/test/MC/Disassembler/X86/prefixes.txt
index 983e09670d68..75e11ae93f4c 100644
--- a/test/MC/Disassembler/X86/prefixes.txt
+++ b/test/MC/Disassembler/X86/prefixes.txt
@@ -1,73 +1,53 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s
-# CHECK: rep
-# CHECK-NEXT: insb %dx, %es:(%rdi)
+# CHECK: rep insb %dx, %es:(%rdi)
0xf3 0x6c #rep ins
-# CHECK: rep
-# CHECK-NEXT: insl %dx, %es:(%rdi)
+# CHECK: rep insl %dx, %es:(%rdi)
0xf3 0x6d #rep ins
-# CHECK: rep
-# CHECK-NEXT: movsb (%rsi), %es:(%rdi)
+# CHECK: rep movsb (%rsi), %es:(%rdi)
0xf3 0xa4 #rep movs
-# CHECK: rep
-# CHECK-NEXT: movsl (%rsi), %es:(%rdi)
+# CHECK: rep movsl (%rsi), %es:(%rdi)
0xf3 0xa5 #rep movs
-# CHECK: rep
-# CHECK-NEXT: outsb (%rsi), %dx
+# CHECK: rep outsb (%rsi), %dx
0xf3 0x6e #rep outs
-# CHECK: rep
-# CHECK-NEXT: outsl (%rsi), %dx
+# CHECK: rep outsl (%rsi), %dx
0xf3 0x6f #rep outs
-# CHECK: rep
-# CHECK-NEXT: lodsb (%rsi), %al
+# CHECK: rep lodsb (%rsi), %al
0xf3 0xac #rep lods
-# CHECK: rep
-# CHECK-NEXT: lodsl (%rsi), %eax
+# CHECK: rep lodsl (%rsi), %eax
0xf3 0xad #rep lods
-# CHECK: rep
-# CHECK-NEXT: stosb %al, %es:(%rdi)
+# CHECK: rep stosb %al, %es:(%rdi)
0xf3 0xaa #rep stos
-# CHECK: rep
-# CHECK-NEXT: stosl %eax, %es:(%rdi)
+# CHECK: rep stosl %eax, %es:(%rdi)
0xf3 0xab #rep stos
-# CHECK: rep
-# CHECK-NEXT: cmpsb %es:(%rdi), (%rsi)
+# CHECK: rep cmpsb %es:(%rdi), (%rsi)
0xf3 0xa6 #rep cmps
-# CHECK: rep
-# CHECK-NEXT: cmpsl %es:(%rdi), (%rsi)
+# CHECK: rep cmpsl %es:(%rdi), (%rsi)
0xf3 0xa7 #repe cmps
-# CHECK: rep
-# CHECK-NEXT: scasb %es:(%rdi), %al
+# CHECK: rep scasb %es:(%rdi), %al
0xf3 0xae #repe scas
-# CHECK: rep
-# CHECK-NEXT: scasl %es:(%rdi), %eax
+# CHECK: rep scasl %es:(%rdi), %eax
0xf3 0xaf #repe scas
-# CHECK: repne
-# CHECK-NEXT: cmpsb %es:(%rdi), (%rsi)
+# CHECK: repne cmpsb %es:(%rdi), (%rsi)
0xf2 0xa6 #repne cmps
-# CHECK: repne
-# CHECK-NEXT: cmpsl %es:(%rdi), (%rsi)
+# CHECK: repne cmpsl %es:(%rdi), (%rsi)
0xf2 0xa7 #repne cmps
-# CHECK: repne
-# CHECK-NEXT: scasb %es:(%rdi), %al
+# CHECK: repne scasb %es:(%rdi), %al
0xf2 0xae #repne scas
-# CHECK: repne
-# CHECK-NEXT: scasl %es:(%rdi), %eax
+# CHECK: repne scasl %es:(%rdi), %eax
0xf2 0xaf #repne scas
# CHECK: lock
-# CHECK-NEXT: orl $16, %fs:776
+# CHECK-NEXT: orl $16, %fs:776
0xf0 0x64 0x83 0x0c 0x25 0x08 0x03 0x00 0x00 0x10
# CHECK: movq %fs:768, %rdi
0x64 0x48 0x8b 0x3c 0x25 0x00 0x03 0x00 0x00
-# CHECK: rep
-# CHECK-NEXT: stosq %rax, %es:(%rdi)
+# CHECK: rep stosq %rax, %es:(%rdi)
0xf3 0x48 0xab
-# CHECK: rep
-# CHECK-NEXT: stosq %rax, %es:(%edi)
+# CHECK: rep stosq %rax, %es:(%edi)
0xf3 0x67 0x48 0xab
# CHECK: movl 32(%rbp), %eax
@@ -104,11 +84,9 @@
0x66,0x83,0xc0,0xf4
# Test that multiple redundant prefixes work (redundant, but valid x86).
-# CHECK: rep
-# CHECK-NEXT: stosq
+# CHECK: rep stosq
0xf3 0xf3 0x48 0xab
-
# Test that we can disassembler control registers above CR8
# CHECK: movq %cr15, %rax
0x44 0x0f 0x20 0xf8
diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt
index 86d9f92fbbfa..390749341647 100644
--- a/test/MC/Disassembler/X86/simple-tests.txt
+++ b/test/MC/Disassembler/X86/simple-tests.txt
@@ -851,14 +851,11 @@
0xf0 0x48 0x0f 0xc1 0xcb
# rdar://13493622 lldb doesn't print the x86 rep/repne prefix when disassembling
-# CHECK: repne
-# CHECK-NEXT: movsl
+# CHECK: repne movsl
0xf2 0xa5
-# CHECK: repne
-# CHECK-NEXT: movsq
+# CHECK: repne movsq
0xf2 0x48 0xa5
-# CHECK: repne
-# CHECK-NEXT: movb $0, (%rax)
+# CHECK: repne movb $0, (%rax)
0xf2 0xc6 0x0 0x0
# rdar://11019859 Support 2013 Haswell RTM instructions and HLE prefixes
diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s
index 66fcf72ec7fb..b47924453cbe 100644
--- a/test/MC/Mips/micromips32r6/valid.s
+++ b/test/MC/Mips/micromips32r6/valid.s
@@ -84,7 +84,7 @@
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
- movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
+ movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x44,0x36]
rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
diff --git a/test/MC/Mips/micromips64r6/valid.s b/test/MC/Mips/micromips64r6/valid.s
index 641e16c14574..a2acedb03c01 100644
--- a/test/MC/Mips/micromips64r6/valid.s
+++ b/test/MC/Mips/micromips64r6/valid.s
@@ -35,7 +35,7 @@ a:
lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
- movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
+ movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x44,0x36]
not16 $4, $7 # CHECK: not16 $4, $7 # encoding: [0x46,0x70]
or16 $3, $7 # CHECK: or16 $3, $7 # encoding: [0x45,0xf9]
ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
diff --git a/test/MC/Mips/tls-symbols.s b/test/MC/Mips/tls-symbols.s
new file mode 100644
index 000000000000..d5a31b189502
--- /dev/null
+++ b/test/MC/Mips/tls-symbols.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -arch=mips < %s -position-independent -filetype=obj \
+# RUN: | llvm-readelf -symbols | FileCheck %s
+# RUN: llvm-mc -arch=mips < %s -filetype=obj | llvm-readelf -symbols \
+# RUN: | FileCheck %s
+
+# Test that TLS relocations cause symbols to be marked as TLS symbols.
+
+ .set noat
+ lui $3, %tlsgd(foo1)
+ lui $1, %dtprel_hi(foo2)
+ lui $1, %dtprel_lo(foo3)
+ lui $1, %tprel_hi(foo4)
+ lui $1, %tprel_lo(foo5)
+ lw $2, %gottprel(foo6)($28)
+
+ .hidden foo1
+ .hidden foo2
+ .hidden foo3
+ .hidden foo4
+ .hidden foo5
+ .hidden foo6
+
+# CHECK: 1: {{.+}} {{.+}} TLS GLOBAL HIDDEN UND foo1
+# CHECK: 2: {{.+}} {{.+}} TLS GLOBAL HIDDEN UND foo2
+# CHECK: 3: {{.+}} {{.+}} TLS GLOBAL HIDDEN UND foo3
+# CHECK: 4: {{.+}} {{.+}} TLS GLOBAL HIDDEN UND foo4
+# CHECK: 5: {{.+}} {{.+}} TLS GLOBAL HIDDEN UND foo5
+# CHECK: 6: {{.+}} {{.+}} TLS GLOBAL HIDDEN UND foo6
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