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path: root/drivers/gpu/drm/i915/i915_reg.h
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* Merge tag 'drm-intel-next-2015-12-18' of git://anongit.freedesktop.org/drm-in...Dave Airlie2015-12-231-3/+3
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| * drm/i915: dual link pipe selection for bxtDeepak M2015-12-111-3/+1
| * drm/i915: Disable CLKOUT_DP bending on LPT/WPT as neededVille Syrjälä2015-12-081-0/+2
* | drm/doc: Convert to markdownDanilo Cesar Lemes de Paula2015-12-151-24/+24
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* drm/i915: Correct the Ref clock value for BXTDeepak M2015-12-041-1/+1
* drm/i915: Don't register the CRT connector when it's fused off on LPT-HVille Syrjälä2015-12-021-0/+1
* drm/i915/bxt: backlight clock gating workaroundImre Deak2015-12-021-0/+7
* drm/i915: Type safe register read/writeVille Syrjälä2015-11-181-1262/+1210
* drm/i915: Add missing ')' to SKL_PS_ECC_STAT defineVille Syrjälä2015-11-181-1/+1
* drm/i915: Give names to more ring registersVille Syrjälä2015-11-181-0/+8
* drm/i915: Make the cmd parser 64bit regs explicitVille Syrjälä2015-11-181-2/+18
* drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctlVille Syrjälä2015-11-181-1/+2
* drm/i915: Parametrize MOCS registersVille Syrjälä2015-11-181-6/+6
* drm/i915: Parametrize L3 error registersVille Syrjälä2015-11-181-4/+2
* drm/i915: Prefix raw register defines with underscoreVille Syrjälä2015-11-181-131/+131
* drm/i915/gen9: Turn DC handling into a power wellPatrik Jakobsson2015-11-171-0/+1
* drm/i915: Explain usage of power well IDs vs bit groupsPatrik Jakobsson2015-11-171-0/+4
* drm/i915/gen9: simplify DC toggling codeImre Deak2015-11-171-0/+1
* drm/i915: fix the power well ID for always on wellsImre Deak2015-11-171-1/+3
* drm/i915: Add dev_priv->psr_mmio_baseVille Syrjälä2015-11-161-7/+8
* drm/i915: Remove the magic AUX_CTL is at DP + foo tricksVille Syrjälä2015-11-161-27/+27
* drm/i915: Parametrize AUX registersVille Syrjälä2015-11-161-50/+52
* drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/Ville Syrjälä2015-11-101-1/+1
* drm/i915: Add csr programming registers to dmc debugfs entryMika Kuoppala2015-11-091-0/+10
* drm/i915/bxt: Expose DC5 entry countMika Kuoppala2015-11-091-0/+1
* drm/i915/skl: Expose DC5/DC6 entry countsDamien Lespiau2015-11-091-0/+4
* drm/i915/skl: While sanitizing cdclock check the SWF18 as wellShobhit Kumar2015-11-051-0/+1
* drm/i915: Use paramtrized WRPLL_CTL()Ville Syrjälä2015-10-261-1/+1
* drm/i915: Parametrize and fix SWF registersVille Syrjälä2015-10-131-14/+14
* drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.Ville Syrjälä2015-10-131-6/+6
* drm/i915: Fix a few bad hex numbers in register definesVille Syrjälä2015-10-131-2/+2
* drm/i915: Protect register macro argumentsVille Syrjälä2015-10-131-46/+46
* drm/i915: Include gpio_mmio_base in GMBUS reg definesVille Syrjälä2015-10-131-6/+6
* drm/i915: Parametrize HSW video DIP data registersVille Syrjälä2015-10-131-8/+8
* drm/i915: Eliminate weird parameter inversion from BXT PPS registersVille Syrjälä2015-10-131-4/+4
* drm/i915/bxt: Set time interval unit to 0.833usAkash Goel2015-10-071-1/+4
* drm/i915: Add GEN7_GPGPU_DISPATCHDIMX/Y/Z to the register whitelistJordan Justen2015-10-061-0/+4
* drm/i915/bxt: Modify BXT BLC according to VBT changesSunil Kamath2015-10-021-8/+20
* drm/i915/bxt: Program Tx Rx and Dphy clocksShashank Sharma2015-10-021-0/+62
* drm/i915/bxt: DSI enable for BXTShashank Sharma2015-10-021-0/+7
* drm/i915: rename INSTDONE1 to GEN4_INSTDONE1Imre Deak2015-10-021-1/+1
* drm/i915: rename INSTDONE to GEN2_INSTDONEImre Deak2015-10-021-1/+2
* drm/i915: remove duplicate names for the render ring INSTDONE registerImre Deak2015-10-021-2/+4
* drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.Ville Syrjälä2015-10-011-2/+2
* drm/i915/bdw: Check for slice, subslice and EU count for BDWŁukasz Daniluk2015-09-301-0/+18
* drm/i915: Read czclk from CCK on vlv/chvVille Syrjälä2015-09-301-0/+1
* drm/i915: Renaming CCK related reg definitionsVandana Kannan2015-09-301-5/+5
* drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASEVille Syrjälä2015-09-301-1/+7
* drm/i915: Parametrize PALETTE and LGC_PALETTEVille Syrjälä2015-09-301-3/+3
* drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSRVille Syrjälä2015-09-301-1/+1
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