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path: root/drivers/clk/tegra/clk-dfll.c
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* clk: tegra: Add closed loop support for the DFLLTuomas Tynkkynen2014-12-061-3/+654
* clk: tegra: Add library for the DFLL clock source (open-loop mode)Tuomas Tynkkynen2014-12-061-0/+1090