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path: root/drivers/clk/sunxi
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* clk: sunxi: fix thinko in commentEmilio López2014-03-191-1/+1
* clk: sunxi: fix some calculationsEmilio López2014-03-191-3/+3
* clk: sunxi: fix A20 PLL4 calculationEmilio López2014-03-191-0/+7
* clk: sunxi: Add new clock compatiblesMaxime Ripard2014-02-181-15/+15
* clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai2014-02-181-0/+96
* clk: sunxi: Add support for PLL6 on the A31Maxime Ripard2014-02-181-0/+45
* clk: sunxi: Add USB clock register defintionsRoman Byshko2014-02-181-0/+12
* clk: sunxi: Add support for USB clock-register reset bitsHans de Goede2014-02-181-0/+71
* clk: sunxi: get divs parent clock name from parent factor clockChen-Yu Tsai2014-02-031-1/+2
* clk: sunxi: add names for pll5, pll6 parent clocks to factors_dataChen-Yu Tsai2014-02-031-9/+18
* clk: sunxi: add clock-output-names dt property supportChen-Yu Tsai2014-02-031-0/+6
* clk: sunxi: fix overflow when setting up divided factorsEmilio López2014-01-271-1/+1
* clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai2013-12-281-0/+57
* clk: sunxi: support better factor DT nodesEmilio López2013-12-281-0/+9
* clk: sunxi: mod0 supportEmilio López2013-12-281-0/+57
* clk: sunxi: add PLL5 and PLL6 supportEmilio López2013-12-281-0/+230
* clk: sunxi: make factors_clk_setup return the clock it registersEmilio López2013-12-281-7/+8
* clk: sunxi: add gating support to PLL1Emilio López2013-12-281-0/+2
* clk: sunxi: clean the magic number of mux parentsEmilio López2013-12-281-2/+3
* clk: sunxi: register factors clocks behind compositeEmilio López2013-12-283-73/+76
* Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into clk-n...Mike Turquette2013-12-012-14/+48
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| * drivers: clk: sunxi: Fix memory leakage in clk-sunxi.cVictor N. Ramos Mello2013-11-101-11/+17
| * clk: sunxi: protect core clocks from accidental shutdownEmilio López2013-11-101-0/+28
| * clk: sunxi: factors: clear variables before using themEmilio López2013-11-101-1/+1
| * clk: sunxi: factors: fix off-by-one masksEmilio López2013-11-101-1/+1
* | clk: sunxi: declare OF clock providerSebastian Hesselbarth2013-09-291-5/+6
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* clk: sunxi: Fix incorrect placement of __initconstSachin Kamat2013-08-271-30/+30
* clk: sunxi: Add Allwinner A20 gatesMaxime Ripard2013-08-261-0/+15
* clk: sunxi: Add A31 clocks supportMaxime Ripard2013-08-261-0/+124
* clk: sunxi: Allow to specify the divider width from the dividers dataMaxime Ripard2013-08-261-11/+13
* clk: sunxi: Rename the structure to prepare the addition of sun6iMaxime Ripard2013-08-261-27/+27
* clk: sunxi: fix initialization of basic clocksEmilio López2013-08-261-8/+3
* clk: sunxi: Add A10s gatesMaxime Ripard2013-08-261-0/+15
* clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan2013-08-191-1/+2
* clk: sunxi: Fix checking return value of clk_register_[composite|factors]Axel Lin2013-08-081-2/+2
* clk: sunxi: "cpu_data" is defined in header files of some architecturesGiacomo A. Catenazzi2013-05-291-2/+2
* clk: sun5i: Add compatibles for Allwinner A13Maxime Ripard2013-05-281-8/+23
* clk: sunxi: Unify oscillator clockEmilio López2013-04-121-7/+26
* clk: sunxi: drop an unnecesary kmallocEmilio López2013-04-041-1/+1
* clk: sunxi: drop CLK_IGNORE_UNUSEDEmilio López2013-04-041-4/+4
* clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gatesEmilio López2013-04-041-0/+88
* clk: sunxi: rename compatible stringsEmilio López2013-03-271-8/+8
* clk: arm: sunxi: Add a new clock driver for sunxi SOCsEmilio López2013-03-274-0/+574
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