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* RISC-V: Add PCIe I/O BAR memory mappingYash Shah2019-10-282-1/+13
* riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley2019-10-285-8/+8
* riscv: fp: add missing __user pointer annotationsPaul Walmsley2019-10-281-2/+2
* riscv: add missing header file includesPaul Walmsley2019-10-2813-0/+17
* riscv: mark some code and data as file-staticPaul Walmsley2019-10-282-2/+2
* riscv: init: merge split string literals in preprocessor directivePaul Walmsley2019-10-281-2/+1
* riscv: add prototypes for assembly language functions from head.SPaul Walmsley2019-10-285-0/+29
* riscv: cleanup do_trap_breakChristoph Hellwig2019-10-251-20/+6
* riscv: cleanup <asm/bug.h>Christoph Hellwig2019-10-231-13/+3
* riscv: Fix undefined reference to vmemmap_populate_basepagesKefeng Wang2019-10-231-1/+1
* riscv: Fix implicit declaration of 'page_to_section'Kefeng Wang2019-10-231-4/+1
* riscv: fix fs/proc/kcore.c compilation with sparsemem enabledDavid Abdurachmanov2019-10-231-2/+0
* RISC-V: fix virtual address overlapped in FIXADDR_START and VMEMMAP_STARTGreentime Hu2019-10-151-8/+8
* riscv: tlbflush: remove confusing comment on local_flush_tlb_all()Paul Walmsley2019-10-141-4/+0
* riscv: dts: HiFive Unleashed: add default chosen/stdout-pathPaul Walmsley2019-10-141-0/+1
* riscv: remove the switch statement in do_trap_break()Vincent Chen2019-10-141-11/+11
* RISC-V: entry: Remove unneeded need_resched() loopValentin Schneider2019-10-091-2/+1
* riscv: Correct the handling of unexpected ebreak in do_trap_break()Vincent Chen2019-10-071-3/+3
* riscv: avoid sending a SIGTRAP to a user thread trapped in WARN()Vincent Chen2019-10-071-1/+1
* riscv: avoid kernel hangs when trapped in BUG()Vincent Chen2019-10-071-3/+3
* riscv: Fix memblock reservation for device tree blobAlbert Ou2019-10-011-1/+11
* RISC-V: Clear load reservations while restoring hart contextsPalmer Dabbelt2019-10-012-1/+21
* Merge tag 'riscv/for-v5.4-rc1-b' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2019-09-279-19/+73
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| * riscv: Avoid interrupts being erroneously enabled in handle_exception()Vincent Chen2019-09-201-1/+5
| * riscv: dts: sifive: Drop "clock-frequency" property of cpu nodesBin Meng2019-09-201-3/+0
| * riscv: dts: sifive: Add ethernet0 to the aliases nodeBin Meng2019-09-201-0/+1
| * RISC-V: Export kernel symbols for kvmAtish Patra2019-09-202-0/+2
| * arch/riscv: disable excess harts before picking main boot hartXiang Wang2019-09-201-3/+5
| * RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfigAnup Patel2019-09-192-0/+22
| * RISC-V: Fix building error when CONFIG_SPARSEMEM_MANUAL=yGreentime Hu2019-09-191-12/+12
| * riscv: dts: Add DT support for SiFive FU540 PWM driverYash Shah2019-09-192-0/+26
* | mm: treewide: clarify pgtable_page_{ctor,dtor}() namingMark Rutland2019-09-261-1/+1
* | riscv: make mmap allocation top-down by defaultAlexandre Ghiti2019-09-241-0/+12
* | mm: consolidate pgtable_cache_init() and pgd_cache_init()Mike Rapoport2019-09-241-5/+0
* | mm: remove quicklist page table cachesNicholas Piggin2019-09-241-4/+0
* | Merge tag 'kbuild-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/masa...Linus Torvalds2019-09-202-1/+2
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| * kbuild: add CONFIG_ASM_MODVERSIONSMasahiro Yamada2019-08-221-0/+1
| * kbuild: rebuild modules when module linker scripts are updatedMasahiro Yamada2019-08-211-1/+1
* | Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2019-09-1624-110/+369
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| * | riscv: move the TLB flush logic out of lineChristoph Hellwig2019-09-053-30/+45
| * | riscv: don't use the rdtime(h) pseudo-instructionsChristoph Hellwig2019-09-051-23/+21
| * | riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig2019-09-054-8/+1
| * | riscv: optimize send_ipi_singleChristoph Hellwig2019-09-051-1/+7
| * | riscv: cleanup send_ipi_maskChristoph Hellwig2019-09-051-9/+7
| * | riscv: refactor the IPI codeChristoph Hellwig2019-09-051-24/+31
| * | riscv: Add support for perf registers samplingMao Han2019-09-054-0/+89
| * | riscv: Add perf callchain supportMao Han2019-09-044-3/+101
| * | riscv: add arch/riscv/KbuildMasahiro Yamada2019-08-302-1/+4
| * | RISC-V: Implement sparsememLogan Gunthorpe2019-08-305-0/+57
| * | riscv: Using CSR numbers to access CSRsBin Meng2019-08-306-21/+16
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