diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/base.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 169 |
1 files changed, 84 insertions, 85 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index b87c56800cfe..9dbec04c050d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -91,7 +91,7 @@ nv4_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv04_fifo_new }, - .gr = nv04_gr_new, + .gr = { 0x00000001, nv04_gr_new }, .sw = nv04_sw_new, }; @@ -112,7 +112,7 @@ nv5_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv04_fifo_new }, - .gr = nv04_gr_new, + .gr = { 0x00000001, nv04_gr_new }, .sw = nv04_sw_new, }; @@ -133,7 +133,7 @@ nv10_chipset = { .timer = { 0x00000001, nv04_timer_new }, .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, - .gr = nv10_gr_new, + .gr = { 0x00000001, nv10_gr_new }, }; static const struct nvkm_device_chip @@ -154,7 +154,7 @@ nv11_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv10_fifo_new }, - .gr = nv15_gr_new, + .gr = { 0x00000001, nv15_gr_new }, .sw = nv10_sw_new, }; @@ -176,7 +176,7 @@ nv15_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv10_fifo_new }, - .gr = nv15_gr_new, + .gr = { 0x00000001, nv15_gr_new }, .sw = nv10_sw_new, }; @@ -198,7 +198,7 @@ nv17_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv17_gr_new, + .gr = { 0x00000001, nv17_gr_new }, .sw = nv10_sw_new, }; @@ -220,7 +220,7 @@ nv18_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv17_gr_new, + .gr = { 0x00000001, nv17_gr_new }, .sw = nv10_sw_new, }; @@ -242,7 +242,7 @@ nv1a_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv10_fifo_new }, - .gr = nv15_gr_new, + .gr = { 0x00000001, nv15_gr_new }, .sw = nv10_sw_new, }; @@ -264,7 +264,7 @@ nv1f_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv17_gr_new, + .gr = { 0x00000001, nv17_gr_new }, .sw = nv10_sw_new, }; @@ -286,7 +286,7 @@ nv20_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv20_gr_new, + .gr = { 0x00000001, nv20_gr_new }, .sw = nv10_sw_new, }; @@ -308,7 +308,7 @@ nv25_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv25_gr_new, + .gr = { 0x00000001, nv25_gr_new }, .sw = nv10_sw_new, }; @@ -330,7 +330,7 @@ nv28_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv25_gr_new, + .gr = { 0x00000001, nv25_gr_new }, .sw = nv10_sw_new, }; @@ -352,7 +352,7 @@ nv2a_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv2a_gr_new, + .gr = { 0x00000001, nv2a_gr_new }, .sw = nv10_sw_new, }; @@ -374,7 +374,7 @@ nv30_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv30_gr_new, + .gr = { 0x00000001, nv30_gr_new }, .sw = nv10_sw_new, }; @@ -396,7 +396,7 @@ nv31_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv30_gr_new, + .gr = { 0x00000001, nv30_gr_new }, .mpeg = nv31_mpeg_new, .sw = nv10_sw_new, }; @@ -419,7 +419,7 @@ nv34_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv34_gr_new, + .gr = { 0x00000001, nv34_gr_new }, .mpeg = nv31_mpeg_new, .sw = nv10_sw_new, }; @@ -442,7 +442,7 @@ nv35_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv35_gr_new, + .gr = { 0x00000001, nv35_gr_new }, .sw = nv10_sw_new, }; @@ -464,7 +464,7 @@ nv36_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv17_fifo_new }, - .gr = nv35_gr_new, + .gr = { 0x00000001, nv35_gr_new }, .mpeg = nv31_mpeg_new, .sw = nv10_sw_new, }; @@ -489,7 +489,7 @@ nv40_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv40_gr_new, + .gr = { 0x00000001, nv40_gr_new }, .mpeg = nv40_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -515,7 +515,7 @@ nv41_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv40_gr_new, + .gr = { 0x00000001, nv40_gr_new }, .mpeg = nv40_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -541,7 +541,7 @@ nv42_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv40_gr_new, + .gr = { 0x00000001, nv40_gr_new }, .mpeg = nv40_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -567,7 +567,7 @@ nv43_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv40_gr_new, + .gr = { 0x00000001, nv40_gr_new }, .mpeg = nv40_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -593,7 +593,7 @@ nv44_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv44_gr_new, + .gr = { 0x00000001, nv44_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -619,7 +619,7 @@ nv45_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv40_gr_new, + .gr = { 0x00000001, nv40_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -645,7 +645,7 @@ nv46_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv44_gr_new, + .gr = { 0x00000001, nv44_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -671,7 +671,7 @@ nv47_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv40_gr_new, + .gr = { 0x00000001, nv40_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -697,7 +697,7 @@ nv49_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv40_gr_new, + .gr = { 0x00000001, nv40_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -723,7 +723,7 @@ nv4a_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv44_gr_new, + .gr = { 0x00000001, nv44_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -749,7 +749,7 @@ nv4b_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv40_gr_new, + .gr = { 0x00000001, nv40_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -775,7 +775,7 @@ nv4c_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv44_gr_new, + .gr = { 0x00000001, nv44_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -801,7 +801,7 @@ nv4e_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv44_gr_new, + .gr = { 0x00000001, nv44_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -830,7 +830,7 @@ nv50_chipset = { .disp = { 0x00000001, nv50_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, nv50_fifo_new }, - .gr = nv50_gr_new, + .gr = { 0x00000001, nv50_gr_new }, .mpeg = nv50_mpeg_new, .pm = nv50_pm_new, .sw = nv50_sw_new, @@ -856,7 +856,7 @@ nv63_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv44_gr_new, + .gr = { 0x00000001, nv44_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -882,7 +882,7 @@ nv67_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv44_gr_new, + .gr = { 0x00000001, nv44_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -908,7 +908,7 @@ nv68_chipset = { .disp = { 0x00000001, nv04_disp_new }, .dma = { 0x00000001, nv04_dma_new }, .fifo = { 0x00000001, nv40_fifo_new }, - .gr = nv44_gr_new, + .gr = { 0x00000001, nv44_gr_new }, .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, .sw = nv10_sw_new, @@ -939,7 +939,7 @@ nv84_chipset = { .disp = { 0x00000001, g84_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = g84_gr_new, + .gr = { 0x00000001, g84_gr_new }, .mpeg = g84_mpeg_new, .pm = g84_pm_new, .sw = nv50_sw_new, @@ -971,7 +971,7 @@ nv86_chipset = { .disp = { 0x00000001, g84_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = g84_gr_new, + .gr = { 0x00000001, g84_gr_new }, .mpeg = g84_mpeg_new, .pm = g84_pm_new, .sw = nv50_sw_new, @@ -1003,7 +1003,7 @@ nv92_chipset = { .disp = { 0x00000001, g84_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = g84_gr_new, + .gr = { 0x00000001, g84_gr_new }, .mpeg = g84_mpeg_new, .pm = g84_pm_new, .sw = nv50_sw_new, @@ -1035,7 +1035,7 @@ nv94_chipset = { .disp = { 0x00000001, g94_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = g84_gr_new, + .gr = { 0x00000001, g84_gr_new }, .mpeg = g84_mpeg_new, .pm = g84_pm_new, .sw = nv50_sw_new, @@ -1067,7 +1067,7 @@ nv96_chipset = { .disp = { 0x00000001, g94_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = g84_gr_new, + .gr = { 0x00000001, g84_gr_new }, .mpeg = g84_mpeg_new, .pm = g84_pm_new, .sw = nv50_sw_new, @@ -1097,7 +1097,7 @@ nv98_chipset = { .disp = { 0x00000001, g94_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = g84_gr_new, + .gr = { 0x00000001, g84_gr_new }, .mspdec = g98_mspdec_new, .msppp = g98_msppp_new, .msvld = g98_msvld_new, @@ -1131,7 +1131,7 @@ nva0_chipset = { .disp = { 0x00000001, gt200_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = gt200_gr_new, + .gr = { 0x00000001, gt200_gr_new }, .mpeg = g84_mpeg_new, .pm = gt200_pm_new, .sw = nv50_sw_new, @@ -1163,7 +1163,7 @@ nva3_chipset = { .disp = { 0x00000001, gt215_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = gt215_gr_new, + .gr = { 0x00000001, gt215_gr_new }, .mpeg = g84_mpeg_new, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, @@ -1197,7 +1197,7 @@ nva5_chipset = { .disp = { 0x00000001, gt215_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = gt215_gr_new, + .gr = { 0x00000001, gt215_gr_new }, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, .msvld = gt215_msvld_new, @@ -1230,7 +1230,7 @@ nva8_chipset = { .disp = { 0x00000001, gt215_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = gt215_gr_new, + .gr = { 0x00000001, gt215_gr_new }, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, .msvld = gt215_msvld_new, @@ -1261,7 +1261,7 @@ nvaa_chipset = { .disp = { 0x00000001, mcp77_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = gt200_gr_new, + .gr = { 0x00000001, gt200_gr_new }, .mspdec = g98_mspdec_new, .msppp = g98_msppp_new, .msvld = g98_msvld_new, @@ -1293,7 +1293,7 @@ nvac_chipset = { .disp = { 0x00000001, mcp77_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = mcp79_gr_new, + .gr = { 0x00000001, mcp79_gr_new }, .mspdec = g98_mspdec_new, .msppp = g98_msppp_new, .msvld = g98_msvld_new, @@ -1327,7 +1327,7 @@ nvaf_chipset = { .disp = { 0x00000001, mcp89_disp_new }, .dma = { 0x00000001, nv50_dma_new }, .fifo = { 0x00000001, g84_fifo_new }, - .gr = mcp89_gr_new, + .gr = { 0x00000001, mcp89_gr_new }, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, .msvld = mcp89_msvld_new, @@ -1363,7 +1363,7 @@ nvc0_chipset = { .disp = { 0x00000001, gt215_disp_new }, .dma = { 0x00000001, gf100_dma_new }, .fifo = { 0x00000001, gf100_fifo_new }, - .gr = gf100_gr_new, + .gr = { 0x00000001, gf100_gr_new }, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1399,7 +1399,7 @@ nvc1_chipset = { .disp = { 0x00000001, gt215_disp_new }, .dma = { 0x00000001, gf100_dma_new }, .fifo = { 0x00000001, gf100_fifo_new }, - .gr = gf108_gr_new, + .gr = { 0x00000001, gf108_gr_new }, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1435,7 +1435,7 @@ nvc3_chipset = { .disp = { 0x00000001, gt215_disp_new }, .dma = { 0x00000001, gf100_dma_new }, .fifo = { 0x00000001, gf100_fifo_new }, - .gr = gf104_gr_new, + .gr = { 0x00000001, gf104_gr_new }, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1471,7 +1471,7 @@ nvc4_chipset = { .disp = { 0x00000001, gt215_disp_new }, .dma = { 0x00000001, gf100_dma_new }, .fifo = { 0x00000001, gf100_fifo_new }, - .gr = gf104_gr_new, + .gr = { 0x00000001, gf104_gr_new }, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1507,7 +1507,7 @@ nvc8_chipset = { .disp = { 0x00000001, gt215_disp_new }, .dma = { 0x00000001, gf100_dma_new }, .fifo = { 0x00000001, gf100_fifo_new }, - .gr = gf110_gr_new, + .gr = { 0x00000001, gf110_gr_new }, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1543,7 +1543,7 @@ nvce_chipset = { .disp = { 0x00000001, gt215_disp_new }, .dma = { 0x00000001, gf100_dma_new }, .fifo = { 0x00000001, gf100_fifo_new }, - .gr = gf104_gr_new, + .gr = { 0x00000001, gf104_gr_new }, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1579,7 +1579,7 @@ nvcf_chipset = { .disp = { 0x00000001, gt215_disp_new }, .dma = { 0x00000001, gf100_dma_new }, .fifo = { 0x00000001, gf100_fifo_new }, - .gr = gf104_gr_new, + .gr = { 0x00000001, gf104_gr_new }, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1614,7 +1614,7 @@ nvd7_chipset = { .disp = { 0x00000001, gf119_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gf100_fifo_new }, - .gr = gf117_gr_new, + .gr = { 0x00000001, gf117_gr_new }, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1650,7 +1650,7 @@ nvd9_chipset = { .disp = { 0x00000001, gf119_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gf100_fifo_new }, - .gr = gf119_gr_new, + .gr = { 0x00000001, gf119_gr_new }, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1687,7 +1687,7 @@ nve4_chipset = { .disp = { 0x00000001, gk104_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gk104_fifo_new }, - .gr = gk104_gr_new, + .gr = { 0x00000001, gk104_gr_new }, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1724,7 +1724,7 @@ nve6_chipset = { .disp = { 0x00000001, gk104_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gk104_fifo_new }, - .gr = gk104_gr_new, + .gr = { 0x00000001, gk104_gr_new }, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1761,7 +1761,7 @@ nve7_chipset = { .disp = { 0x00000001, gk104_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gk104_fifo_new }, - .gr = gk104_gr_new, + .gr = { 0x00000001, gk104_gr_new }, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1789,7 +1789,7 @@ nvea_chipset = { .ce = { 0x00000004, gk104_ce_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gk20a_fifo_new }, - .gr = gk20a_gr_new, + .gr = { 0x00000001, gk20a_gr_new }, .pm = gk104_pm_new, .sw = gf100_sw_new, }; @@ -1823,7 +1823,7 @@ nvf0_chipset = { .disp = { 0x00000001, gk110_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gk110_fifo_new }, - .gr = gk110_gr_new, + .gr = { 0x00000001, gk110_gr_new }, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1859,7 +1859,7 @@ nvf1_chipset = { .disp = { 0x00000001, gk110_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gk110_fifo_new }, - .gr = gk110b_gr_new, + .gr = { 0x00000001, gk110b_gr_new }, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1895,7 +1895,7 @@ nv106_chipset = { .disp = { 0x00000001, gk110_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gk208_fifo_new }, - .gr = gk208_gr_new, + .gr = { 0x00000001, gk208_gr_new }, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1931,7 +1931,7 @@ nv108_chipset = { .disp = { 0x00000001, gk110_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gk208_fifo_new }, - .gr = gk208_gr_new, + .gr = { 0x00000001, gk208_gr_new }, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1967,7 +1967,7 @@ nv117_chipset = { .disp = { 0x00000001, gm107_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gm107_fifo_new }, - .gr = gm107_gr_new, + .gr = { 0x00000001, gm107_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sw = gf100_sw_new, @@ -2002,7 +2002,7 @@ nv118_chipset = { .disp = { 0x00000001, gm107_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gm107_fifo_new }, - .gr = gm107_gr_new, + .gr = { 0x00000001, gm107_gr_new }, .sw = gf100_sw_new, }; @@ -2035,7 +2035,7 @@ nv120_chipset = { .disp = { 0x00000001, gm200_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gm200_fifo_new }, - .gr = gm200_gr_new, + .gr = { 0x00000001, gm200_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, @@ -2071,7 +2071,7 @@ nv124_chipset = { .disp = { 0x00000001, gm200_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gm200_fifo_new }, - .gr = gm200_gr_new, + .gr = { 0x00000001, gm200_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, @@ -2107,7 +2107,7 @@ nv126_chipset = { .disp = { 0x00000001, gm200_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gm200_fifo_new }, - .gr = gm200_gr_new, + .gr = { 0x00000001, gm200_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sw = gf100_sw_new, @@ -2134,7 +2134,7 @@ nv12b_chipset = { .ce = { 0x00000004, gm200_ce_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gm20b_fifo_new }, - .gr = gm20b_gr_new, + .gr = { 0x00000001, gm20b_gr_new }, .sw = gf100_sw_new, }; @@ -2165,7 +2165,7 @@ nv130_chipset = { .dma = { 0x00000001, gf119_dma_new }, .disp = { 0x00000001, gp100_disp_new }, .fifo = { 0x00000001, gp100_fifo_new }, - .gr = gp100_gr_new, + .gr = { 0x00000001, gp100_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, @@ -2200,7 +2200,7 @@ nv132_chipset = { .disp = { 0x00000001, gp102_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gp100_fifo_new }, - .gr = gp102_gr_new, + .gr = { 0x00000001, gp102_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, @@ -2235,7 +2235,7 @@ nv134_chipset = { .disp = { 0x00000001, gp102_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gp100_fifo_new }, - .gr = gp104_gr_new, + .gr = { 0x00000001, gp104_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, @@ -2270,7 +2270,7 @@ nv136_chipset = { .disp = { 0x00000001, gp102_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gp100_fifo_new }, - .gr = gp104_gr_new, + .gr = { 0x00000001, gp104_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = gp102_sec2_new, @@ -2304,7 +2304,7 @@ nv137_chipset = { .disp = { 0x00000001, gp102_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gp100_fifo_new }, - .gr = gp107_gr_new, + .gr = { 0x00000001, gp107_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, @@ -2339,7 +2339,7 @@ nv138_chipset = { .disp = { 0x00000001, gp102_disp_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gp100_fifo_new }, - .gr = gp108_gr_new, + .gr = { 0x00000001, gp108_gr_new }, .nvdec[0] = gm107_nvdec_new, .sec2 = gp108_sec2_new, .sw = gf100_sw_new, @@ -2365,7 +2365,7 @@ nv13b_chipset = { .ce = { 0x00000001, gp100_ce_new }, .dma = { 0x00000001, gf119_dma_new }, .fifo = { 0x00000001, gp10b_fifo_new }, - .gr = gp10b_gr_new, + .gr = { 0x00000001, gp10b_gr_new }, .sw = gf100_sw_new, }; @@ -2397,7 +2397,7 @@ nv140_chipset = { .disp = { 0x00000001, gv100_disp_new }, .dma = { 0x00000001, gv100_dma_new }, .fifo = { 0x00000001, gv100_fifo_new }, - .gr = gv100_gr_new, + .gr = { 0x00000001, gv100_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, @@ -2433,7 +2433,7 @@ nv162_chipset = { .disp = { 0x00000001, tu102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, .fifo = { 0x00000001, tu102_fifo_new }, - .gr = tu102_gr_new, + .gr = { 0x00000001, tu102_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, @@ -2467,7 +2467,7 @@ nv164_chipset = { .disp = { 0x00000001, tu102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, .fifo = { 0x00000001, tu102_fifo_new }, - .gr = tu102_gr_new, + .gr = { 0x00000001, tu102_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvdec[1] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, @@ -2502,7 +2502,7 @@ nv166_chipset = { .disp = { 0x00000001, tu102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, .fifo = { 0x00000001, tu102_fifo_new }, - .gr = tu102_gr_new, + .gr = { 0x00000001, tu102_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvdec[1] = gm107_nvdec_new, .nvdec[2] = gm107_nvdec_new, @@ -2538,7 +2538,7 @@ nv167_chipset = { .disp = { 0x00000001, tu102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, .fifo = { 0x00000001, tu102_fifo_new }, - .gr = tu102_gr_new, + .gr = { 0x00000001, tu102_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, @@ -2572,7 +2572,7 @@ nv168_chipset = { .disp = { 0x00000001, tu102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, .fifo = { 0x00000001, tu102_fifo_new }, - .gr = tu102_gr_new, + .gr = { 0x00000001, tu102_gr_new }, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, @@ -3174,7 +3174,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func, #include <core/layout.h> #undef NVKM_LAYOUT_INST #undef NVKM_LAYOUT_ONCE - _(NVKM_ENGINE_GR , gr); _(NVKM_ENGINE_IFB , ifb); _(NVKM_ENGINE_ME , me); _(NVKM_ENGINE_MPEG , mpeg); |