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authorSumit Gupta <sumitg@nvidia.com>2022-05-12 01:46:43 +0530
committerThierry Reding <treding@nvidia.com>2022-09-15 12:30:11 +0200
commit96765cc47546fe6724825600afa8ba170671da61 (patch)
tree03e36c95fb199e8d0687ce6423ec47998b6e4986 /include
parent568035b01cfb107af8d2e4bd2fb9aea22cf5b868 (diff)
downloadlinux-96765cc47546fe6724825600afa8ba170671da61.tar.gz
soc/tegra: Set ERD bit to mask inband errors
Add a function to set the ERD (Error Response Disable) bit in the MISCREG_CCROC_ERR_CONFIG register from the Control Backbone (CBB) error handler driver. ERD bit allows masking of SError due to inband errors which are caused by illegal register accesses through CBB. When the bit is set, interrupt is used for reporting errors and magic code '0xdead2003' is returned. This change is only required for Tegra194 SoC as the config is moved to CBB register space for future SoC's. Also, remove unmapping the apbmisc_base as it's required to get the base address for accessing the misc register. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/soc/tegra/fuse.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
index 67d2bc856fbc..977c334136e9 100644
--- a/include/soc/tegra/fuse.h
+++ b/include/soc/tegra/fuse.h
@@ -58,6 +58,7 @@ u32 tegra_read_chipid(void);
u8 tegra_get_chip_id(void);
u8 tegra_get_platform(void);
bool tegra_is_silicon(void);
+int tegra194_miscreg_mask_serror(void);
#else
static struct tegra_sku_info tegra_sku_info __maybe_unused;
@@ -95,6 +96,11 @@ static inline bool tegra_is_silicon(void)
{
return false;
}
+
+static inline int tegra194_miscreg_mask_serror(void)
+{
+ return false;
+}
#endif
struct device *tegra_soc_device_register(void);