diff options
| author | Ludovic Barre <ludovic.barre@st.com> | 2018-10-08 14:08:52 +0200 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2018-10-09 09:13:04 +0200 |
| commit | 00e930d87d196ae70e225eee88957441c10ff872 (patch) | |
| tree | 1c57b0715577d330fa4c6bc0d51593002bffedce /drivers | |
| parent | 15878e58461bbb4def541b72b835be410e1a9cf4 (diff) | |
| download | linux-00e930d87d196ae70e225eee88957441c10ff872.tar.gz | |
mmc: mmci: add clock divider for stm32 sdmmc
The STM32 sdmmc variant has a different clock divider.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/host/mmci.c | 2 | ||||
| -rw-r--r-- | drivers/mmc/host/mmci.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index d636a0e6aa9f..ad2f62fc0af8 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -1862,6 +1862,8 @@ static int mmci_probe(struct amba_device *dev, */ if (variant->st_clkdiv) mmc->f_min = DIV_ROUND_UP(host->mclk, 257); + else if (variant->stm32_clkdiv) + mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); else if (variant->explicit_mclk_control) mmc->f_min = clk_round_rate(host->clk, 100000); else diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index 8ecb1eee001e..a962cfa339a3 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -216,6 +216,7 @@ struct mmci_host; * @data_cmd_enable: enable value for data commands. * @st_sdio: enable ST specific SDIO logic * @st_clkdiv: true if using a ST-specific clock divider algorithm + * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl @@ -269,6 +270,7 @@ struct variant_data { u8 datacnt_useless:1; u8 st_sdio:1; u8 st_clkdiv:1; + u8 stm32_clkdiv:1; u8 blksz_datactrl16:1; u8 blksz_datactrl4:1; u32 pwrreg_powerup; |