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| author | Dong Aisheng <aisheng.dong@nxp.com> | 2017-05-19 15:05:42 +0800 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-05-22 11:03:47 +0200 |
| commit | a5cadbbb081cb84a9fdb14391fb461a41f089a0a (patch) | |
| tree | e9999bdde75f877b3bdf0e2ac36438851a7c78ef /drivers/pinctrl/freescale/pinctrl-imx.h | |
| parent | 66b54e3a5a64925d9819eae86b8f36e90e60037f (diff) | |
| download | linux-a5cadbbb081cb84a9fdb14391fb461a41f089a0a.tar.gz | |
pinctrl: imx: add generic pin config core support
The design is based on the exist architecture that the core will
provide a uniformed way to decode the generic pin config into platform
config register raw data according to the imx_cfg_params_decode maps
registered by platform.
Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT,
are created for platform to register decode map conveniently.
In order to cope with some special case, a platform specific fixup()
function is also available to use.
Note that rather than fully utilizing the generic pinconf support
provided by pinctrl core, IMX only adopts the device tree bindings
of generic pinconf. The config used in .pin_config_get[set] are raw
register data instead of generic one which makes us align the exist
using. And that's also why we cannot set pinconf_ops.is_generic.
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/freescale/pinctrl-imx.h')
| -rw-r--r-- | drivers/pinctrl/freescale/pinctrl-imx.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index ff2d3e56b7c5..38aa53c671ed 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -15,6 +15,8 @@ #ifndef __DRIVERS_PINCTRL_IMX_H #define __DRIVERS_PINCTRL_IMX_H +#include <linux/pinctrl/pinconf-generic.h> + struct platform_device; /** @@ -44,6 +46,14 @@ struct imx_pin_reg { s16 conf_reg; }; +/* decode a generic config into raw register value */ +struct imx_cfg_params_decode { + enum pin_config_param param; + u32 mask; + u8 shift; + bool invert; +}; + struct imx_pinctrl_soc_info { struct device *dev; const struct pinctrl_pin_desc *pins; @@ -53,8 +63,23 @@ struct imx_pinctrl_soc_info { unsigned int flags; const char *gpr_compatible; struct mutex mutex; + + /* generic pinconf */ + bool generic_pinconf; + const struct pinconf_generic_params *custom_params; + unsigned int num_custom_params; + struct imx_cfg_params_decode *decodes; + unsigned int num_decodes; + void (*fixup)(unsigned long *configs, unsigned int num_configs, + u32 *raw_config); }; +#define IMX_CFG_PARAMS_DECODE(p, m, o) \ + { .param = p, .mask = m, .shift = o, .invert = false, } + +#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \ + { .param = p, .mask = m, .shift = o, .invert = true, } + #define SHARE_MUX_CONF_REG 0x1 #define ZERO_OFFSET_VALID 0x2 |