diff options
| author | Nadeem Athani <nadeem@cadence.com> | 2021-02-09 15:46:21 +0100 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2021-02-10 12:48:45 +0000 |
| commit | 4740b969aaf58adeca6829947a3ad8da423976cf (patch) | |
| tree | 1d1980fd69098195242074bab9e9313e15e12bb6 /drivers/pci/controller/cadence/pci-j721e.c | |
| parent | 7c53f6b671f4aba70ff15e1b05148b10d58c2837 (diff) | |
| download | linux-4740b969aaf58adeca6829947a3ad8da423976cf.tar.gz | |
PCI: cadence: Retrain Link to work around Gen2 training defect
Cadence controller will not initiate autonomous speed change if strapped
as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
Link: https://lore.kernel.org/r/20210209144622.26683-3-nadeem@cadence.com
Signed-off-by: Nadeem Athani <nadeem@cadence.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/cadence/pci-j721e.c')
| -rw-r--r-- | drivers/pci/controller/cadence/pci-j721e.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index dac1ac8a7615..849f1e416ea5 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -64,6 +64,7 @@ enum j721e_pcie_mode { struct j721e_pcie_data { enum j721e_pcie_mode mode; + bool quirk_retrain_flag; }; static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) @@ -280,6 +281,7 @@ static struct pci_ops cdns_ti_pcie_host_ops = { static const struct j721e_pcie_data j721e_pcie_rc_data = { .mode = PCI_MODE_RC, + .quirk_retrain_flag = true, }; static const struct j721e_pcie_data j721e_pcie_ep_data = { @@ -388,6 +390,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) bridge->ops = &cdns_ti_pcie_host_ops; rc = pci_host_bridge_priv(bridge); + rc->quirk_retrain_flag = data->quirk_retrain_flag; cdns_pcie = &rc->pcie; cdns_pcie->dev = dev; |