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authorDmitry Osipenko <digetx@gmail.com>2019-08-12 00:00:41 +0300
committerThierry Reding <treding@nvidia.com>2019-11-11 14:55:27 +0100
commit77b7182ff18dd5a83d938ab42772db5cb82c75b8 (patch)
tree84d19c1cb768c754b27c22394e6da63c19b00bad /drivers/memory
parente34212c75a68990f7215d64d725c61e57ca70357 (diff)
downloadlinux-77b7182ff18dd5a83d938ab42772db5cb82c75b8.tar.gz
memory: tegra: Ensure timing control debug features are disabled
Timing control debug features should be disabled at a boot time, but you never now and hence it's better to disable them explicitly because some of those features are crucial for the driver to do a proper thing. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory')
-rw-r--r--drivers/memory/tegra/mc.c3
-rw-r--r--drivers/memory/tegra/mc.h2
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 41ee420275f1..a1f9a0506048 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -667,6 +667,9 @@ static int tegra_mc_probe(struct platform_device *pdev)
} else
#endif
{
+ /* ensure that debug features are disabled */
+ mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG);
+
err = tegra_mc_setup_latency_allowance(mc);
if (err < 0) {
dev_err(&pdev->dev,
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index 410efc4d7e7b..cd52628c2b96 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -30,6 +30,8 @@
#define MC_EMEM_ARB_OVERRIDE 0xe8
#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3
+#define MC_TIMING_CONTROL_DBG 0xf8
+
#define MC_TIMING_CONTROL 0xfc
#define MC_TIMING_UPDATE BIT(0)