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| author | Thierry Reding <treding@nvidia.com> | 2022-01-12 09:40:34 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2022-03-01 11:13:09 +0100 |
| commit | 28aa30b08de6f4b346f25f7c8bb5ba3739c1879c (patch) | |
| tree | 732c7af0eb157c9957ce4371ba97c5f1bd3a6842 /drivers/gpu/drm/tegra/hub.c | |
| parent | 025c6643a81564f066d8381b9e2f4603e0f8438f (diff) | |
| download | linux-28aa30b08de6f4b346f25f7c8bb5ba3739c1879c.tar.gz | |
drm/tegra: Fix planar formats on Tegra186 and later
Use the correct pitch when programming the DC_WIN_PLANAR_STORAGE_UV
register's PITCH_U field to ensure the correct value is used in all
cases. This isn't currently causing any problems because the pitch
for both U and V planes is always the same.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/hub.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/hub.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c index b910155f80c4..fc9813e6b2c9 100644 --- a/drivers/gpu/drm/tegra/hub.c +++ b/drivers/gpu/drm/tegra/hub.c @@ -673,7 +673,7 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane, tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V); tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V); - value = PITCH_U(fb->pitches[2]) | PITCH_V(fb->pitches[2]); + value = PITCH_U(fb->pitches[1]) | PITCH_V(fb->pitches[2]); tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV); } else { tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_U); |