diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2015-10-01 11:36:58 +1000 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2015-11-03 15:02:18 +1000 |
commit | c4266a9c7b0ee66b3d1ca22745d8eb9472e21b4b (patch) | |
tree | 34c766ab46b8fa9b5b8b4cdea50763f33a1e4d83 /drivers/gpu/drm/nouveau/nvkm/subdev/pci | |
parent | b31505c472f2451c6143bf4727e79ea177a35ca5 (diff) | |
download | linux-c4266a9c7b0ee66b3d1ca22745d8eb9472e21b4b.tar.gz |
drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by default
Was not able to obtain a trace of NVRM due to kernel version annoyances,
however, experimentally confirmed that the WAR we use on NV50/G8x boards
works here too.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/subdev/pci')
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv50.c) | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h | 2 |
4 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild index 85cb52501ada..4476ef75acd6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild @@ -2,8 +2,8 @@ nvkm-y += nvkm/subdev/pci/agp.o nvkm-y += nvkm/subdev/pci/base.o nvkm-y += nvkm/subdev/pci/nv04.o nvkm-y += nvkm/subdev/pci/nv40.o +nvkm-y += nvkm/subdev/pci/nv46.o nvkm-y += nvkm/subdev/pci/nv4c.o -nvkm-y += nvkm/subdev/pci/nv50.o nvkm-y += nvkm/subdev/pci/g84.o nvkm-y += nvkm/subdev/pci/g94.o nvkm-y += nvkm/subdev/pci/gf100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c index 30be277edf2a..8f3b00199d14 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c @@ -30,7 +30,7 @@ g84_pci_func = { .rd32 = nv40_pci_rd32, .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, - .msi_rearm = nv50_pci_msi_rearm, + .msi_rearm = nv46_pci_msi_rearm, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c index 027481519ff9..fc617e4c0ab6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c @@ -25,11 +25,11 @@ #include <core/pci.h> -/* MSI re-arm through the PRI appears to be broken on NV50/G84/G86/G92, +/* MSI re-arm through the PRI appears to be broken on NV46/NV50/G84/G86/G92, * so we access it via alternate PCI config space mechanisms. */ void -nv50_pci_msi_rearm(struct nvkm_pci *pci) +nv46_pci_msi_rearm(struct nvkm_pci *pci) { struct nvkm_device *device = pci->subdev.device; struct pci_dev *pdev = device->func->pci(device)->pdev; @@ -37,15 +37,15 @@ nv50_pci_msi_rearm(struct nvkm_pci *pci) } static const struct nvkm_pci_func -nv50_pci_func = { +nv46_pci_func = { .rd32 = nv40_pci_rd32, .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, - .msi_rearm = nv50_pci_msi_rearm, + .msi_rearm = nv46_pci_msi_rearm, }; int -nv50_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +nv46_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) { - return nvkm_pci_new_(&nv50_pci_func, device, index, ppci); + return nvkm_pci_new_(&nv46_pci_func, device, index, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h index 68ce8e554ae9..473b8ab25351 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h @@ -18,5 +18,5 @@ void nv40_pci_wr08(struct nvkm_pci *, u16, u8); void nv40_pci_wr32(struct nvkm_pci *, u16, u32); void nv40_pci_msi_rearm(struct nvkm_pci *); -void nv50_pci_msi_rearm(struct nvkm_pci *); +void nv46_pci_msi_rearm(struct nvkm_pci *); #endif |