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authorDave Airlie <airlied@redhat.com>2022-02-11 14:13:36 +1000
committerDave Airlie <airlied@redhat.com>2022-02-11 14:14:07 +1000
commite7a09cea6483b44ea0c82f07145fcbd8a918bf96 (patch)
tree825489ab7bf8347cfac7b2e3eccf9138ed75d624 /drivers/gpu/drm/i915/display/g4x_dp.c
parent53dbee4926d3706ca9e03f3928fa85b5ec3bc0cc (diff)
parent7938f4218168ae9fc4bdddb15976f9ebbae41999 (diff)
downloadlinux-e7a09cea6483b44ea0c82f07145fcbd8a918bf96.tar.gz
Merge tag 'drm-intel-next-2022-02-08' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
Cross-subsystem Changes: ------------------------ dma-buf: - dma-buf-map: Rename to iosys-map (Lucas) Core Changes: ------------- drm: - Always include the debugfs_entry in drm_crtc (Ville) - Add orientation quirk for GPD Win Max (Anisse) Driver Changes: --------------- gvt: - Constify some pointers. (Rikard Falkeborn) - Use list_entry to access list members. (Guenter Roeck) - Fix cmd parser error for Passmark9. (Zhenyu Wang) i915: - Various clean-ups including headers and removing unused and unnecessary stuff\ (Jani, Hans, Andy, Ville) - Cleaning up on our registers definitions i915_reg.h (Matt) - More multi-FBC refactoring (Ville) - Baytrail backlight fix (Hans) - DG1 OPROM read through SPI controller (Clint) - ADL-N platform enabling (Tejas) - Fix slab-out-of-bounds access (Jani) - Add opregion mailbox #5 support for possible EDID override (Anisse) - Fix possible NULL dereferences (Harish) - Updates and fixes around display voltage swing values (Clint, Jose) - Fix RPM wekeref on PXP code (Juston) - Many register definitions clean-up, including planes registers (Ville) - More conversion towards display version over the old gen (Madhumitha, Ville) - DP MST ESI handling improvements (Jani) - drm device based logging conversions (Jani) - Prevent divide by zero (Dan) - Introduce ilk_pch_pre_enable for complete modeset abstraction (Ville) - Async flip optimization for DG2 (Stanislav) - Multiple DSC and bigjoiner fixes and improvements (Ville) - Fix ADL-P TypeC Phy ready status readout (Imre) - Fix up DP DFP 4:2:0 handling more display related fixes (Ville) - Display M/N cleanup (Ville) - Switch to use VGA definitions from video/vga.h (Jani) - Fixes and improvements to abstract CPU architecture (Lucas) - Disable unsused power wells left enabled by BIOS (Imre) - Allow !join_mbus cases for adlp+ dbuf configuration (Ville) - Populate pipe dbuf slices more accurately during readout (Ville) - Workaround broken BIOS DBUF configuration on TGL/RKL (Ville) - Fix trailing semicolon (Lucas) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/YgKFLmCgpv4vQEa1@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/g4x_dp.c')
-rw-r--r--drivers/gpu/drm/i915/display/g4x_dp.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index f37677df6ebf..f67bbaaad8e0 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -18,6 +18,7 @@
#include "intel_fifo_underrun.h"
#include "intel_hdmi.h"
#include "intel_hotplug.h"
+#include "intel_pch_display.h"
#include "intel_pps.h"
#include "vlv_sideband.h"
@@ -333,6 +334,21 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
return ret;
}
+static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->has_pch_encoder) {
+ intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n);
+ intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2);
+ } else {
+ intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
+ &crtc_state->dp_m_n);
+ intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder,
+ &crtc_state->dp_m2_n2);
+ }
+}
+
static void intel_dp_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -384,7 +400,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
pipe_config->lane_count =
((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
- intel_dp_get_m_n(crtc, pipe_config);
+ g4x_dp_get_m_n(pipe_config);
if (port == PORT_A) {
if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)