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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-11-30 11:24:50 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-11-30 19:06:33 +0100
commitacd15b6cc20f85bcef9e08b6ed4f142c34791c32 (patch)
treefe310c1485fbf25a5c36853817e50bee94411edb /drivers/gpu/drm/drm_mm.c
parent99057c81037ee45e94e5c7e6b403b73caccbaf9e (diff)
downloadlinux-acd15b6cc20f85bcef9e08b6ed4f142c34791c32.tar.gz
drm/i915: optimize ilk/snb irq handler
We only need to read/write the south interrupt register if the corresponding bit is set in the north master interrupt register. Noticed while reading our interrupt handling code. Same optimization has already been applied on ivb in commit 0e43406bcc1868a316eea6012a0a09d992c53521 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Wed May 9 21:45:44 2012 +0100 drm/i915: Simplify interrupt processing for IvyBridge We can take advantage that the PCH_IIR is a subordinate register to reduce one of the required IIR reads, and that we only need to clear interrupts handled to reduce the writes. And by simply tidying the code we can reduce the line count and hopefully make it more readable. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/drm_mm.c')
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