diff options
author | Dan Williams <dan.j.williams@intel.com> | 2022-06-06 13:32:01 -0700 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2022-07-25 12:18:07 -0700 |
commit | 6aa41144e7f1a624062f1e66a4744c168ade1f31 (patch) | |
tree | dbc9e873fca39bb4db419da9edc33573b28339a9 /drivers/cxl/cxlmem.h | |
parent | b9686e8c8e39d4072081ef078c04915ee51c8af4 (diff) | |
download | linux-6aa41144e7f1a624062f1e66a4744c168ade1f31.tar.gz |
cxl/acpi: Add a host-bridge index lookup mechanism
The ACPI CXL Fixed Memory Window Structure (CFMWS) defines multiple
methods to determine which host bridge provides access to a given
endpoint relative to that device's position in the interleave. The
"Interleave Arithmetic" defines either a "standard modulo" /
round-random algorithm, or "xormap" based algorithm which can be defined
as a non-linear transform. Given that there are already more options
beyond "standard modulo" and that "xormap" may turn out to be ACPI CXL
specific, provide a callback for the region provisioning code to map
endpoint positions back to expected host bridge id (cxl_dport target).
For now just support the simple modulo math case and save the xormap for
a follow-on change.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20220624041950.559155-14-dan.j.williams@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxlmem.h')
0 files changed, 0 insertions, 0 deletions