diff options
| author | Jiang Liu <jiang.liu@linux.intel.com> | 2014-06-10 14:13:25 +0800 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2014-06-21 23:05:42 +0200 |
| commit | 6b9fb7082409cd4a2c7caf43e3c023ad82dad0d4 (patch) | |
| tree | 0e6fa36575e9b41bde22b2e8414ae0d157105051 /arch/x86/kernel/apic | |
| parent | 4b92b4f754939e4ac6bb53355abbe48a5054b573 (diff) | |
| download | linux-6b9fb7082409cd4a2c7caf43e3c023ad82dad0d4.tar.gz | |
x86, ACPI, irq: Consolidate algorithm of mapping (ioapic, pin) to IRQ number
Currently ACPI and ioapic both implement algorithms to map (ioapic, pin)
to IRQ number. So consolidate the common part into one place, which is
also preparing for irqdomain support.
It introduces mp_map_gsi_to_irq(), which will be used to allocate IRQ
number IOAPIC pins when irqdomain is enabled.
Also rename gsi_to_irq() to map_gsi_to_irq(), later we will introduce
unmap_gsi_to_irq() when enabling IOAPIC hotplug.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Len Brown <len.brown@intel.com>
Cc: Pavel Machek <pavel@ucw.cz>
Link: http://lkml.kernel.org/r/1402380812-32446-1-git-send-email-jiang.liu@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/kernel/apic')
| -rw-r--r-- | arch/x86/kernel/apic/io_apic.c | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index e25e7e315d4f..7fd9f1befe0b 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -959,11 +959,19 @@ static int irq_trigger(int idx) return trigger; } +int mp_map_gsi_to_irq(u32 gsi) +{ + /* + * Provide an identity mapping of gsi == irq except on truly weird + * platforms that have non isa irqs in the first 16 gsis. + */ + return gsi >= nr_legacy_irqs() ? gsi : gsi_top + gsi; +} + static int pin_2_irq(int idx, int apic, int pin) { int irq; int bus = mp_irqs[idx].srcbus; - struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic); /* * Debugging check, we are in big trouble if this message pops up! @@ -971,17 +979,6 @@ static int pin_2_irq(int idx, int apic, int pin) if (mp_irqs[idx].dstirq != pin) pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); - if (test_bit(bus, mp_bus_not_pci)) { - irq = mp_irqs[idx].srcbusirq; - } else { - u32 gsi = gsi_cfg->gsi_base + pin; - - if (gsi >= nr_legacy_irqs()) - irq = gsi; - else - irq = gsi_top + gsi; - } - #ifdef CONFIG_X86_32 /* * PCI IRQ command line redirection. Yes, limits are hardcoded. @@ -996,11 +993,17 @@ static int pin_2_irq(int idx, int apic, int pin) apic_printk(APIC_VERBOSE, KERN_DEBUG "using PIRQ%d -> IRQ %d\n", pin-16, irq); + return irq; } } } #endif + if (test_bit(bus, mp_bus_not_pci)) + irq = mp_irqs[idx].srcbusirq; + else + irq = mp_map_gsi_to_irq(mp_pin_to_gsi(apic, pin)); + return irq; } |