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authorDavid S. Miller <davem@sunset.davemloft.net>2006-02-07 16:09:12 -0800
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 01:11:54 -0800
commit8591e3027235d6d11b958e43379f2ee7b7114841 (patch)
treece3f036ac64e20f7d75bae04e5362c97bc9228e6 /arch/sparc64/kernel/head.S
parentdf7d6aec96ab98cb182dd5138a85bdc363a9bf0d (diff)
downloadlinux-8591e3027235d6d11b958e43379f2ee7b7114841.tar.gz
[SPARC64]: Niagara copy/clear page.
Happily we have no D-cache aliasing issues on these chips, so the implementation is very straightforward. Add a stub in bootup which will be where the patching calls will be made for niagara/sun4v/hypervisor. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/head.S')
-rw-r--r--arch/sparc64/kernel/head.S18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S
index 03fc0b5b1d98..f04f7391f236 100644
--- a/arch/sparc64/kernel/head.S
+++ b/arch/sparc64/kernel/head.S
@@ -316,6 +316,24 @@ sun4u_init:
ba,pt %xcc, spitfire_tlb_fixup
nop
+ /* XXX Nothing branches to here yet, when %ver register indicates
+ * XXX Niagara we should do this.
+ */
+niagara_tlb_fixup:
+ mov 3, %g2 /* Set TLB type to hypervisor. */
+ sethi %hi(tlb_type), %g1
+ stw %g2, [%g1 + %lo(tlb_type)]
+
+ /* Patch copy/clear ops. */
+ call niagara_patch_copyops
+ nop
+ call niagara_patch_pageops
+ nop
+
+ /* Patch TLB/cache ops. */
+ call hypervisor_patch_cachetlbops
+ nop
+
cheetah_tlb_fixup:
mov 2, %g2 /* Set TLB type to cheetah+. */
BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)