diff options
| author | Peng Fan <peng.fan@nxp.com> | 2020-03-11 17:02:06 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2020-03-16 09:18:29 +0800 |
| commit | f5d35d87ef061172a25252b2b5402c972b16d3be (patch) | |
| tree | 1cd6ec8d5014a25e6ccd3efcaba1fddcbe8ec20f /arch/arm/boot/dts/imx6sll.dtsi | |
| parent | 98670a0bb0ef14bbb3df8542e59e0e6106c0ba53 (diff) | |
| download | linux-f5d35d87ef061172a25252b2b5402c972b16d3be.tar.gz | |
ARM: dts: imx: add nvmem property for cpu0
Add nvmem related property for cpu0, then nvmem API could be used
to read cpu speed grading to avoid directly read OCOTP registers
mapped which could not handle defer probe.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6sll.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sll.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index e8e0fb334cfb..edd3abb9a9f1 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -72,6 +72,8 @@ <&clks IMX6SLL_CLK_PLL1_SYS>; clock-names = "arm", "pll2_pfd2_396m", "step", "pll1_sw", "pll1_sys"; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; }; @@ -791,6 +793,10 @@ reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SLL_CLK_OCOTP>; + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + tempmon_calib: calib@38 { reg = <0x38 4>; }; |