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| author | Thierry Reding <thierry.reding@avionic-design.de> | 2012-10-01 08:41:23 +0200 |
|---|---|---|
| committer | Thierry Reding <thierry.reding@avionic-design.de> | 2012-10-07 12:11:53 +0200 |
| commit | 85f8879ca4f3d26a7f473522101fb74a79bda3f2 (patch) | |
| tree | 26bc8e984bb47a8a154fabd58c6642fe9facd882 /Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | |
| parent | c2d476a98f71c55e9acdca1d5a1080a22c0622af (diff) | |
| download | linux-85f8879ca4f3d26a7f473522101fb74a79bda3f2.tar.gz | |
pwm: dt: Fix description of second PWM cell
The second cell in the PWM specifier denotes the period in nanoseconds,
not the duty cycle. The latter can be freely configured at runtime and
a PWM with a fixed duty cycle would be rather pointless.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index bbbeedb4ec05..01438ecd6628 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -7,7 +7,7 @@ Required properties: - reg: physical base address and length of the controller's registers - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The first cell specifies the per-chip index of the PWM to use and the second - cell is the duty cycle in nanoseconds. + cell is the period in nanoseconds. Example: |