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| author | Eric Anholt <eric@anholt.net> | 2015-03-23 19:26:42 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2015-06-04 14:15:32 -0700 |
| commit | 4f81f084ab1707f64659b8c1f2aecedc9fec5659 (patch) | |
| tree | b88a4543d5d645b43deb1a99f1a869710af9d9a6 | |
| parent | 97a9c41ccdb7a7f1b6808583b9c3f6ca7c32ff3d (diff) | |
| download | linux-4f81f084ab1707f64659b8c1f2aecedc9fec5659.tar.gz | |
drm/vc4: Make alignment of raster texture widths more consistent.
This more like how the simulator writes the aligment, and consistent
with the other tiling formats.
Signed-off-by: Eric Anholt <eric@anholt.net>
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_validate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c index 5ecd640f625a..27eabcbb8351 100644 --- a/drivers/gpu/drm/vc4/vc4_validate.c +++ b/drivers/gpu/drm/vc4/vc4_validate.c @@ -164,7 +164,7 @@ check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo, switch (tiling_format) { case VC4_TILING_FORMAT_LINEAR: - aligned_width = roundup(width, 16 / cpp); + aligned_width = roundup(width, utile_w); aligned_height = height; break; case VC4_TILING_FORMAT_T: @@ -951,7 +951,7 @@ reloc_tex(struct vc4_exec_info *exec, aligned_height = roundup(level_height, utile_h); break; default: - aligned_width = roundup(level_width, 16 / cpp); + aligned_width = roundup(level_width, utile_w); aligned_height = level_height; break; } |