summaryrefslogtreecommitdiff
path: root/drivers/clk/ingenic
Commit message (Expand)AuthorAgeFilesLines
* clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_ratePaul Cercueil2020-10-131-0/+2
* clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENTPaul Cercueil2020-10-131-7/+7
* clk: ingenic: Don't use CLK_SET_RATE_GATE for PLLPaul Cercueil2020-10-131-2/+7
* clk: ingenic: Use readl_poll_timeout instead of custom loopPaul Cercueil2020-10-131-26/+29
* clk: ingenic: Use to_clk_info() macro for all clocksPaul Cercueil2020-10-131-39/+15
* clk: X1000: Add support for calculat REFCLK of USB PHY.周琰杰 (Zhou Yanjie)2020-07-271-1/+83
* clk: JZ4780: Reformat the code to align it.周琰杰 (Zhou Yanjie)2020-07-271-45/+45
* clk: JZ4780: Add functions for enable and disable USB PHY.周琰杰 (Zhou Yanjie)2020-07-271-30/+35
* clk: Ingenic: Add RTC related clocks for Ingenic SoCs.周琰杰 (Zhou Yanjie)2020-07-273-0/+38
* clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unusedStephen Boyd2020-05-281-1/+1
* clk: X1000: Add FIXDIV for SSI clock of X1000.周琰杰 (Zhou Yanjie)2020-05-281-6/+111
* clk: Ingenic: Add CGU driver for X1830.周琰杰 (Zhou Yanjie)2020-05-283-0/+459
* clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)2020-05-287-4/+41
* clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)2020-05-281-11/+1
* clk: ingenic/TCU: Fix round_rate returning errorPaul Cercueil2020-03-201-1/+1
* clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil2020-03-201-1/+3
* clk: JZ4780: Add function for enable the second core.周琰杰 (Zhou Yanjie)2020-03-201-5/+50
* clk: Ingenic: Add support for TCU of X1000.周琰杰 (Zhou Yanjie)2020-03-201-0/+8
*-. Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...Stephen Boyd2019-11-273-1/+286
|\ \
| * | clk: ingenic: Allow drivers to be built with COMPILE_TESTStephen Boyd2019-11-221-1/+1
| * | clk: Ingenic: Add CGU driver for X1000.Zhou Yanjie2019-11-133-0/+285
| |/
* | drivers/clk: convert VL struct to struct_sizeStephen Kitt2019-11-081-2/+1
|/
* Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds2019-09-224-1/+490
|\
| * clk: jz4740: Add TCU clockPaul Cercueil2019-08-081-0/+6
| * clk: ingenic: Add driver for the TCU clocksPaul Cercueil2019-08-083-1/+484
* | clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil2019-08-124-4/+4
* | clk: ingenic/jz4740: Fix "pll half" divider not read/written properlyPaul Cercueil2019-08-071-1/+8
|/
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-179-128/+192
|\
| * clk: ingenic: Remove unused functionsPaul Cercueil2019-06-251-73/+0
| * clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil2019-06-257-32/+69
| * clk: ingenic: Add missing header in cgu.hPaul Cercueil2019-06-251-0/+1
| * clk: ingenic/jz4725b: Fix "pll half" divider not read/written properlyPaul Cercueil2019-06-071-1/+8
| * clk: ingenic/jz4725b: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-5/+24
| * clk: ingenic/jz4770: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-6/+28
| * clk: ingenic/jz4740: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-5/+24
| * clk: ingenic: Add support for divider tablesPaul Cercueil2019-06-072-6/+38
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-304-40/+4
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-212-0/+2
|/
* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-154-0/+4
* clk: ingenic: jz4725b: Add UDC PHY clockPaul Cercueil2019-04-111-0/+6
* clk: ingenic: Remove set but not used variable 'enable'YueHaibing2019-02-261-2/+1
* clk: ingenic: Fix doc of ingenic_cgu_div_infoPaul Cercueil2019-02-221-1/+1
* clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil2019-02-221-5/+5
* clk: ingenic: jz4740: Fix gating of UDC clockPaul Cercueil2019-02-051-1/+1
* clk: Add Ingenic jz4725b CGU driverPaul Cercueil2018-10-163-0/+236
* clk: ingenic: Add proper Kconfig entriesPaul Cercueil2018-10-162-4/+41
* clk: ingenic: Add missing flag for UDC clockPaul Cercueil2018-07-061-1/+1
* clk: ingenic: Fix incorrect data for the i2s clockPaul Cercueil2018-07-061-1/+1
* docs: Fix some broken referencesMauro Carvalho Chehab2018-06-151-1/+1
* clk: ingenic: jz4770: Add 150us delay after enabling VPU clockPaul Cercueil2018-06-011-1/+1
View Lorry Controller Status