Commit message (Expand) | Author | Age | Files | Lines | |
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* | RISC-V: Use Linux logical CPU number instead of hartid | Atish Patra | 2018-10-22 | 1 | -3/+13 |
* | riscv: use NULL instead of a plain 0 | Luc Van Oostenryck | 2018-06-07 | 1 | -1/+1 |
* | RISC-V: Limit the scope of TLB shootdowns | Andrew Waterman | 2018-01-30 | 1 | -8/+12 |
* | riscv: remove CONFIG_MMU ifdefs | Christoph Hellwig | 2018-01-07 | 1 | -4/+0 |
* | RISC-V: User-Visible Changes | Palmer Dabbelt | 2017-12-01 | 1 | -0/+2 |
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| * | RISC-V: Flush I$ when making a dirty page executable | Andrew Waterman | 2017-11-30 | 1 | -0/+2 |
* | | RISC-V: `sfence.vma` orderes the instruction cache | Palmer Dabbelt | 2017-11-28 | 1 | -1/+4 |
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* | RISC-V: Atomic and Locking Code | Palmer Dabbelt | 2017-09-26 | 1 | -0/+64 |