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path: root/arch/riscv/include/asm/tlbflush.h
Commit message (Expand)AuthorAgeFilesLines
* RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-221-3/+13
* riscv: use NULL instead of a plain 0Luc Van Oostenryck2018-06-071-1/+1
* RISC-V: Limit the scope of TLB shootdownsAndrew Waterman2018-01-301-8/+12
* riscv: remove CONFIG_MMU ifdefsChristoph Hellwig2018-01-071-4/+0
* RISC-V: User-Visible ChangesPalmer Dabbelt2017-12-011-0/+2
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| * RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2017-11-301-0/+2
* | RISC-V: `sfence.vma` orderes the instruction cachePalmer Dabbelt2017-11-281-1/+4
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* RISC-V: Atomic and Locking CodePalmer Dabbelt2017-09-261-0/+64