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-rw-r--r--sound/soc/codecs/Kconfig6
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/rt1316-sdw.c2
-rw-r--r--sound/soc/codecs/rt1318-sdw.c884
-rw-r--r--sound/soc/codecs/rt1318-sdw.h101
-rw-r--r--sound/soc/codecs/rt711-sdca-sdw.c2
-rw-r--r--sound/soc/codecs/rt715-sdca-sdw.c2
-rw-r--r--sound/soc/codecs/wcd938x-sdw.c1039
-rw-r--r--sound/soc/codecs/wcd938x.c1003
-rw-r--r--sound/soc/codecs/wcd938x.h1
-rw-r--r--sound/soc/codecs/wsa881x.c2
-rw-r--r--sound/soc/codecs/wsa883x.c2
-rw-r--r--sound/soc/intel/common/soc-acpi-intel-byt-match.c2
-rw-r--r--sound/usb/caiaq/input.c1
14 files changed, 2031 insertions, 1018 deletions
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 3f16ad1c3758..965ae55fa160 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -199,6 +199,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_RT715_SDCA_SDW
imply SND_SOC_RT1308_SDW
imply SND_SOC_RT1316_SDW
+ imply SND_SOC_RT1318_SDW
imply SND_SOC_RT9120
imply SND_SOC_SDW_MOCKUP
imply SND_SOC_SGTL5000
@@ -1311,6 +1312,11 @@ config SND_SOC_RT1316_SDW
depends on SOUNDWIRE
select REGMAP_SOUNDWIRE
+config SND_SOC_RT1318_SDW
+ tristate "Realtek RT1318 Codec - SDW"
+ depends on SOUNDWIRE
+ select REGMAP_SOUNDWIRE
+
config SND_SOC_RT5514
tristate
depends on I2C
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 9170ee1447dd..71d3ce5867e4 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -196,6 +196,7 @@ snd-soc-rt1305-objs := rt1305.o
snd-soc-rt1308-objs := rt1308.o
snd-soc-rt1308-sdw-objs := rt1308-sdw.o
snd-soc-rt1316-sdw-objs := rt1316-sdw.o
+snd-soc-rt1318-sdw-objs := rt1318-sdw.o
snd-soc-rt274-objs := rt274.o
snd-soc-rt286-objs := rt286.o
snd-soc-rt298-objs := rt298.o
@@ -551,6 +552,7 @@ obj-$(CONFIG_SND_SOC_RT1305) += snd-soc-rt1305.o
obj-$(CONFIG_SND_SOC_RT1308) += snd-soc-rt1308.o
obj-$(CONFIG_SND_SOC_RT1308_SDW) += snd-soc-rt1308-sdw.o
obj-$(CONFIG_SND_SOC_RT1316_SDW) += snd-soc-rt1316-sdw.o
+obj-$(CONFIG_SND_SOC_RT1318_SDW) += snd-soc-rt1318-sdw.o
obj-$(CONFIG_SND_SOC_RT274) += snd-soc-rt274.o
obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o
obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o
diff --git a/sound/soc/codecs/rt1316-sdw.c b/sound/soc/codecs/rt1316-sdw.c
index ed0a11436362..154b6179b6dc 100644
--- a/sound/soc/codecs/rt1316-sdw.c
+++ b/sound/soc/codecs/rt1316-sdw.c
@@ -585,7 +585,7 @@ static int rt1316_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
* slave_ops: callbacks for get_clock_stop_mode, clock_stop and
* port_prep are not defined for now
*/
-static struct sdw_slave_ops rt1316_slave_ops = {
+static const struct sdw_slave_ops rt1316_slave_ops = {
.read_prop = rt1316_read_prop,
.update_status = rt1316_update_status,
};
diff --git a/sound/soc/codecs/rt1318-sdw.c b/sound/soc/codecs/rt1318-sdw.c
new file mode 100644
index 000000000000..c6ec86e97a6e
--- /dev/null
+++ b/sound/soc/codecs/rt1318-sdw.c
@@ -0,0 +1,884 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// rt1318-sdw.c -- rt1318 SDCA ALSA SoC amplifier audio driver
+//
+// Copyright(c) 2022 Realtek Semiconductor Corp.
+//
+//
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/pm_runtime.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/dmi.h>
+#include <linux/firmware.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include "rt1318-sdw.h"
+
+static const struct reg_sequence rt1318_blind_write[] = {
+ { 0xc001, 0x43 },
+ { 0xc003, 0xa2 },
+ { 0xc004, 0x44 },
+ { 0xc005, 0x44 },
+ { 0xc006, 0x33 },
+ { 0xc007, 0x64 },
+ { 0xc320, 0x20 },
+ { 0xf203, 0x18 },
+ { 0xf211, 0x00 },
+ { 0xf212, 0x26 },
+ { 0xf20d, 0x17 },
+ { 0xf214, 0x06 },
+ { 0xf20e, 0x00 },
+ { 0xf223, 0x7f },
+ { 0xf224, 0xdb },
+ { 0xf225, 0xee },
+ { 0xf226, 0x3f },
+ { 0xf227, 0x0f },
+ { 0xf21a, 0x78 },
+ { 0xf242, 0x3c },
+ { 0xc321, 0x0b },
+ { 0xc200, 0xd8 },
+ { 0xc201, 0x27 },
+ { 0xc202, 0x0f },
+ { 0xf800, 0x20 },
+ { 0xdf00, 0x10 },
+ { 0xdf5f, 0x01 },
+ { 0xdf60, 0xa7 },
+ { 0xc400, 0x0e },
+ { 0xc401, 0x43 },
+ { 0xc402, 0xe0 },
+ { 0xc403, 0x00 },
+ { 0xc404, 0x4c },
+ { 0xc407, 0x02 },
+ { 0xc408, 0x3f },
+ { 0xc300, 0x01 },
+ { 0xc206, 0x78 },
+ { 0xc203, 0x84 },
+ { 0xc120, 0xc0 },
+ { 0xc121, 0x03 },
+ { 0xe000, 0x88 },
+ { 0xc321, 0x09 },
+ { 0xc322, 0x01 },
+ { 0xe706, 0x0f },
+ { 0xe707, 0x30 },
+ { 0xe806, 0x0f },
+ { 0xe807, 0x30 },
+ { 0xed00, 0xb0 },
+ { 0xce04, 0x02 },
+ { 0xce05, 0x63 },
+ { 0xce06, 0x68 },
+ { 0xce07, 0x07 },
+ { 0xcf04, 0x02 },
+ { 0xcf05, 0x63 },
+ { 0xcf06, 0x68 },
+ { 0xcf07, 0x07 },
+ { 0xce60, 0xe3 },
+ { 0xc130, 0x51 },
+ { 0xf102, 0x00 },
+ { 0xf103, 0x00 },
+ { 0xf104, 0xf5 },
+ { 0xf105, 0x06 },
+ { 0xf109, 0x9b },
+ { 0xf10a, 0x0b },
+ { 0xf10b, 0x4c },
+ { 0xf10b, 0x5c },
+ { 0xf102, 0x00 },
+ { 0xf103, 0x00 },
+ { 0xf104, 0xf5 },
+ { 0xf105, 0x0b },
+ { 0xf109, 0x03 },
+ { 0xf10a, 0x0b },
+ { 0xf10b, 0x4c },
+ { 0xf10b, 0x5c },
+ { 0xf102, 0x00 },
+ { 0xf103, 0x00 },
+ { 0xf104, 0xf5 },
+ { 0xf105, 0x0c },
+ { 0xf109, 0x7f },
+ { 0xf10a, 0x0b },
+ { 0xf10b, 0x4c },
+ { 0xf10b, 0x5c },
+
+ { 0xe604, 0x00 },
+ { 0xdb00, 0x0c },
+ { 0xdd00, 0x0c },
+ { 0xdc19, 0x00 },
+ { 0xdc1a, 0xff },
+ { 0xdc1b, 0xff },
+ { 0xdc1c, 0xff },
+ { 0xdc1d, 0x00 },
+ { 0xdc1e, 0x00 },
+ { 0xdc1f, 0x00 },
+ { 0xdc20, 0xff },
+ { 0xde19, 0x00 },
+ { 0xde1a, 0xff },
+ { 0xde1b, 0xff },
+ { 0xde1c, 0xff },
+ { 0xde1d, 0x00 },
+ { 0xde1e, 0x00 },
+ { 0xde1f, 0x00 },
+ { 0xde20, 0xff },
+ { 0xdb32, 0x00 },
+ { 0xdd32, 0x00 },
+ { 0xdb33, 0x0a },
+ { 0xdd33, 0x0a },
+ { 0xdb34, 0x1a },
+ { 0xdd34, 0x1a },
+ { 0xdb17, 0xef },
+ { 0xdd17, 0xef },
+ { 0xdba7, 0x00 },
+ { 0xdba8, 0x64 },
+ { 0xdda7, 0x00 },
+ { 0xdda8, 0x64 },
+ { 0xdb19, 0x40 },
+ { 0xdd19, 0x40 },
+ { 0xdb00, 0x4c },
+ { 0xdb01, 0x79 },
+ { 0xdd01, 0x79 },
+ { 0xdb04, 0x05 },
+ { 0xdb05, 0x03 },
+ { 0xdd04, 0x05 },
+ { 0xdd05, 0x03 },
+ { 0xdbbb, 0x09 },
+ { 0xdbbc, 0x30 },
+ { 0xdbbd, 0xf0 },
+ { 0xdbbe, 0xf1 },
+ { 0xddbb, 0x09 },
+ { 0xddbc, 0x30 },
+ { 0xddbd, 0xf0 },
+ { 0xddbe, 0xf1 },
+ { 0xdb01, 0x79 },
+ { 0xdd01, 0x79 },
+ { 0xdc52, 0xef },
+ { 0xde52, 0xef },
+ { 0x2f55, 0x22 },
+};
+
+static const struct reg_default rt1318_reg_defaults[] = {
+ { 0x3000, 0x00 },
+ { 0x3004, 0x01 },
+ { 0x3005, 0x23 },
+ { 0x3202, 0x00 },
+ { 0x3203, 0x01 },
+ { 0x3206, 0x00 },
+ { 0xc000, 0x00 },
+ { 0xc001, 0x43 },
+ { 0xc003, 0x22 },
+ { 0xc004, 0x44 },
+ { 0xc005, 0x44 },
+ { 0xc006, 0x33 },
+ { 0xc007, 0x64 },
+ { 0xc008, 0x05 },
+ { 0xc00a, 0xfc },
+ { 0xc00b, 0x0f },
+ { 0xc00c, 0x0e },
+ { 0xc00d, 0xef },
+ { 0xc00e, 0xe5 },
+ { 0xc00f, 0xff },
+ { 0xc120, 0xc0 },
+ { 0xc121, 0x00 },
+ { 0xc122, 0x00 },
+ { 0xc123, 0x14 },
+ { 0xc125, 0x00 },
+ { 0xc200, 0x00 },
+ { 0xc201, 0x00 },
+ { 0xc202, 0x00 },
+ { 0xc203, 0x04 },
+ { 0xc204, 0x00 },
+ { 0xc205, 0x00 },
+ { 0xc206, 0x68 },
+ { 0xc207, 0x70 },
+ { 0xc208, 0x00 },
+ { 0xc20a, 0x00 },
+ { 0xc20b, 0x01 },
+ { 0xc20c, 0x7f },
+ { 0xc20d, 0x01 },
+ { 0xc20e, 0x7f },
+ { 0xc300, 0x00 },
+ { 0xc301, 0x00 },
+ { 0xc303, 0x80 },
+ { 0xc320, 0x00 },
+ { 0xc321, 0x09 },
+ { 0xc322, 0x02 },
+ { 0xc410, 0x04 },
+ { 0xc430, 0x00 },
+ { 0xc431, 0x00 },
+ { 0xca00, 0x10 },
+ { 0xca01, 0x00 },
+ { 0xca02, 0x0b },
+ { 0xca10, 0x10 },
+ { 0xca11, 0x00 },
+ { 0xca12, 0x0b },
+ { 0xdd93, 0x00 },
+ { 0xdd94, 0x64 },
+ { 0xe300, 0xa0 },
+ { 0xed00, 0x80 },
+ { 0xed01, 0x0f },
+ { 0xed02, 0xff },
+ { 0xed03, 0x00 },
+ { 0xed04, 0x00 },
+ { 0xed05, 0x0f },
+ { 0xed06, 0xff },
+ { 0xf010, 0x10 },
+ { 0xf011, 0xec },
+ { 0xf012, 0x68 },
+ { 0xf013, 0x21 },
+ { 0xf800, 0x00 },
+ { 0xf801, 0x12 },
+ { 0xf802, 0xe0 },
+ { 0xf803, 0x2f },
+ { 0xf804, 0x00 },
+ { 0xf805, 0x00 },
+ { 0xf806, 0x07 },
+ { 0xf807, 0xff },
+ { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 },
+ { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L), 0x01 },
+ { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R), 0x01 },
+ { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23, RT1318_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
+ { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
+};
+
+static bool rt1318_readable_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case 0x2f55:
+ case 0x3000:
+ case 0x3004 ... 0x3005:
+ case 0x3202 ... 0x3203:
+ case 0x3206:
+ case 0xc000 ... 0xc00f:
+ case 0xc120 ... 0xc125:
+ case 0xc200 ... 0xc20e:
+ case 0xc300 ... 0xc303:
+ case 0xc320 ... 0xc322:
+ case 0xc410:
+ case 0xc430 ... 0xc431:
+ case 0xca00 ... 0xca02:
+ case 0xca10 ... 0xca12:
+ case 0xcb00 ... 0xcb0b:
+ case 0xcc00 ... 0xcce5:
+ case 0xcd00 ... 0xcde5:
+ case 0xce00 ... 0xce6a:
+ case 0xcf00 ... 0xcf53:
+ case 0xd000 ... 0xd0cc:
+ case 0xd100 ... 0xd1b9:
+ case 0xdb00 ... 0xdc53:
+ case 0xdd00 ... 0xde53:
+ case 0xdf00 ... 0xdf6b:
+ case 0xe300:
+ case 0xeb00 ... 0xebcc:
+ case 0xec00 ... 0xecb9:
+ case 0xed00 ... 0xed06:
+ case 0xf010 ... 0xf014:
+ case 0xf800 ... 0xf807:
+ case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0):
+ case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L):
+ case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R):
+ case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23, RT1318_SDCA_CTL_REQ_POWER_STATE, 0):
+ case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
+ case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
+ case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool rt1318_volatile_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case 0x2f55:
+ case 0x3000 ... 0x3001:
+ case 0xc000:
+ case 0xc301:
+ case 0xc410:
+ case 0xc430 ... 0xc431:
+ case 0xdb06:
+ case 0xdb12:
+ case 0xdb1d ... 0xdb1f:
+ case 0xdb35:
+ case 0xdb37:
+ case 0xdb8a ... 0xdb92:
+ case 0xdbc5 ... 0xdbc8:
+ case 0xdc2b ... 0xdc49:
+ case 0xdd0b:
+ case 0xdd12:
+ case 0xdd1d ... 0xdd1f:
+ case 0xdd35:
+ case 0xdd8a ... 0xdd92:
+ case 0xddc5 ... 0xddc8:
+ case 0xde2b ... 0xde44:
+ case 0xdf4a ... 0xdf55:
+ case 0xe224 ... 0xe23b:
+ case 0xea01:
+ case 0xebc5:
+ case 0xebc8:
+ case 0xebcb ... 0xebcc:
+ case 0xed03 ... 0xed06:
+ case 0xf010 ... 0xf014:
+ case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
+ case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
+ return true;
+ default:
+ return false;
+ }
+}
+
+static const struct regmap_config rt1318_sdw_regmap = {
+ .reg_bits = 32,
+ .val_bits = 8,
+ .readable_reg = rt1318_readable_register,
+ .volatile_reg = rt1318_volatile_register,
+ .max_register = 0x41081488,
+ .reg_defaults = rt1318_reg_defaults,
+ .num_reg_defaults = ARRAY_SIZE(rt1318_reg_defaults),
+ .cache_type = REGCACHE_RBTREE,
+ .use_single_read = true,
+ .use_single_write = true,
+};
+
+static int rt1318_read_prop(struct sdw_slave *slave)
+{
+ struct sdw_slave_prop *prop = &slave->prop;
+ int nval;
+ int i, j;
+ u32 bit;
+ unsigned long addr;
+ struct sdw_dpn_prop *dpn;
+
+ prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
+ prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
+ prop->is_sdca = true;
+
+ prop->paging_support = true;
+
+ /* first we need to allocate memory for set bits in port lists */
+ prop->source_ports = BIT(2);
+ prop->sink_ports = BIT(1);
+
+ nval = hweight32(prop->source_ports);
+ prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
+ sizeof(*prop->src_dpn_prop), GFP_KERNEL);
+ if (!prop->src_dpn_prop)
+ return -ENOMEM;
+
+ i = 0;
+ dpn = prop->src_dpn_prop;
+ addr = prop->source_ports;
+ for_each_set_bit(bit, &addr, 32) {
+ dpn[i].num = bit;
+ dpn[i].type = SDW_DPN_FULL;
+ dpn[i].simple_ch_prep_sm = true;
+ dpn[i].ch_prep_timeout = 10;
+ i++;
+ }
+
+ /* do this again for sink now */
+ nval = hweight32(prop->sink_ports);
+ prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
+ sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
+ if (!prop->sink_dpn_prop)
+ return -ENOMEM;
+
+ j = 0;
+ dpn = prop->sink_dpn_prop;
+ addr = prop->sink_ports;
+ for_each_set_bit(bit, &addr, 32) {
+ dpn[j].num = bit;
+ dpn[j].type = SDW_DPN_FULL;
+ dpn[j].simple_ch_prep_sm = true;
+ dpn[j].ch_prep_timeout = 10;
+ j++;
+ }
+
+ /* set the timeout values */
+ prop->clk_stop_timeout = 20;
+
+ return 0;
+}
+
+static int rt1318_io_init(struct device *dev, struct sdw_slave *slave)
+{
+ struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev);
+
+ if (rt1318->hw_init)
+ return 0;
+
+ if (rt1318->first_hw_init) {
+ regcache_cache_only(rt1318->regmap, false);
+ regcache_cache_bypass(rt1318->regmap, true);
+ } else {
+ /*
+ * PM runtime is only enabled when a Slave reports as Attached
+ */
+
+ /* set autosuspend parameters */
+ pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
+ pm_runtime_use_autosuspend(&slave->dev);
+
+ /* update count of parent 'active' children */
+ pm_runtime_set_active(&slave->dev);
+
+ /* make sure the device does not suspend immediately */
+ pm_runtime_mark_last_busy(&slave->dev);
+
+ pm_runtime_enable(&slave->dev);
+ }
+
+ pm_runtime_get_noresume(&slave->dev);
+
+ /* blind write */
+ regmap_multi_reg_write(rt1318->regmap, rt1318_blind_write,
+ ARRAY_SIZE(rt1318_blind_write));
+
+ if (rt1318->first_hw_init) {
+ regcache_cache_bypass(rt1318->regmap, false);
+ regcache_mark_dirty(rt1318->regmap);
+ }
+
+ /* Mark Slave initialization complete */
+ rt1318->first_hw_init = true;
+ rt1318->hw_init = true;
+
+ pm_runtime_mark_last_busy(&slave->dev);
+ pm_runtime_put_autosuspend(&slave->dev);
+
+ dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
+ return 0;
+}
+
+static int rt1318_update_status(struct sdw_slave *slave,
+ enum sdw_slave_status status)
+{
+ struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(&slave->dev);
+
+ /* Update the status */
+ rt1318->status = status;
+
+ if (status == SDW_SLAVE_UNATTACHED)
+ rt1318->hw_init = false;
+
+ /*
+ * Perform initialization only if slave status is present and
+ * hw_init flag is false
+ */
+ if (rt1318->hw_init || rt1318->status != SDW_SLAVE_ATTACHED)
+ return 0;
+
+ /* perform I/O transfers required for Slave initialization */
+ return rt1318_io_init(&slave->dev, slave);
+}
+
+static int rt1318_classd_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_component *component =
+ snd_soc_dapm_to_component(w->dapm);
+ struct rt1318_sdw_priv *rt1318 = snd_soc_component_get_drvdata(component);
+ unsigned char ps0 = 0x0, ps3 = 0x3;
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ regmap_write(rt1318->regmap,
+ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23,
+ RT1318_SDCA_CTL_REQ_POWER_STATE, 0),
+ ps0);
+ break;
+ case SND_SOC_DAPM_PRE_PMD:
+ regmap_write(rt1318->regmap,
+ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23,
+ RT1318_SDCA_CTL_REQ_POWER_STATE, 0),
+ ps3);
+ break;
+
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static const char * const rt1318_rx_data_ch_select[] = {
+ "L,R",
+ "L,L",
+ "L,R",
+ "L,L+R",
+ "R,L",
+ "R,R",
+ "R,L+R",
+ "L+R,L",
+ "L+R,R",
+ "L+R,L+R",
+};
+
+static SOC_ENUM_SINGLE_DECL(rt1318_rx_data_ch_enum,
+ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0), 0,
+ rt1318_rx_data_ch_select);
+
+static const struct snd_kcontrol_new rt1318_snd_controls[] = {
+
+ /* UDMPU Cluster Selection */
+ SOC_ENUM("RX Channel Select", rt1318_rx_data_ch_enum),
+};
+
+static const struct snd_kcontrol_new rt1318_sto_dac =
+ SOC_DAPM_DOUBLE_R("Switch",
+ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L),
+ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R),
+ 0, 1, 1);
+
+static const struct snd_soc_dapm_widget rt1318_dapm_widgets[] = {
+ /* Audio Interface */
+ SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
+
+ /* Digital Interface */
+ SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1318_sto_dac),
+
+ /* Output */
+ SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
+ rt1318_classd_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_OUTPUT("SPOL"),
+ SND_SOC_DAPM_OUTPUT("SPOR"),
+ /* Input */
+ SND_SOC_DAPM_PGA("FB Data", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_SIGGEN("FB Gen"),
+};
+
+static const struct snd_soc_dapm_route rt1318_dapm_routes[] = {
+ { "DAC", "Switch", "DP1RX" },
+ { "CLASS D", NULL, "DAC" },
+ { "SPOL", NULL, "CLASS D" },
+ { "SPOR", NULL, "CLASS D" },
+
+ { "FB Data", NULL, "FB Gen" },
+ { "DP2TX", NULL, "FB Data" },
+};
+
+static int rt1318_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
+ int direction)
+{
+ struct sdw_stream_data *stream;
+
+ if (!sdw_stream)
+ return 0;
+
+ stream = kzalloc(sizeof(*stream), GFP_KERNEL);
+ if (!stream)
+ return -ENOMEM;
+
+ stream->sdw_stream = sdw_stream;
+
+ /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
+ if (direction == SNDRV_PCM_STREAM_PLAYBACK)
+ dai->playback_dma_data = stream;
+ else
+ dai->capture_dma_data = stream;
+
+ return 0;
+}
+
+static void rt1318_sdw_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct sdw_stream_data *stream;
+
+ stream = snd_soc_dai_get_dma_data(dai, substream);
+ snd_soc_dai_set_dma_data(dai, substream, NULL);
+ kfree(stream);
+}
+
+static int rt1318_sdw_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+ struct snd_soc_component *component = dai->component;
+ struct rt1318_sdw_priv *rt1318 =
+ snd_soc_component_get_drvdata(component);
+ struct sdw_stream_config stream_config;
+ struct sdw_port_config port_config;
+ enum sdw_data_direction direction;
+ struct sdw_stream_data *stream;
+ int retval, port, num_channels, ch_mask;
+ unsigned int sampling_rate;
+
+ dev_dbg(dai->dev, "%s %s", __func__, dai->name);
+ stream = snd_soc_dai_get_dma_data(dai, substream);
+
+ if (!stream)
+ return -EINVAL;
+
+ if (!rt1318->sdw_slave)
+ return -EINVAL;
+
+ /* SoundWire specific configuration */
+ /* port 1 for playback */
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ direction = SDW_DATA_DIR_RX;
+ port = 1;
+ } else {
+ direction = SDW_DATA_DIR_TX;
+ port = 2;
+ }
+
+ num_channels = params_channels(params);
+ ch_mask = (1 << num_channels) - 1;
+
+ stream_config.frame_rate = params_rate(params);
+ stream_config.ch_count = num_channels;
+ stream_config.bps = snd_pcm_format_width(params_format(params));
+ stream_config.direction = direction;
+
+ port_config.ch_mask = ch_mask;
+ port_config.num = port;
+
+ retval = sdw_stream_add_slave(rt1318->sdw_slave, &stream_config,
+ &port_config, 1, stream->sdw_stream);
+ if (retval) {
+ dev_err(dai->dev, "Unable to configure port\n");
+ return retval;
+ }
+
+ /* sampling rate configuration */
+ switch (params_rate(params)) {
+ case 16000:
+ sampling_rate = RT1318_SDCA_RATE_16000HZ;
+ break;
+ case 32000:
+ sampling_rate = RT1318_SDCA_RATE_32000HZ;
+ break;
+ case 44100:
+ sampling_rate = RT1318_SDCA_RATE_44100HZ;
+ break;
+ case 48000:
+ sampling_rate = RT1318_SDCA_RATE_48000HZ;
+ break;
+ case 96000:
+ sampling_rate = RT1318_SDCA_RATE_96000HZ;
+ break;
+ case 192000:
+ sampling_rate = RT1318_SDCA_RATE_192000HZ;
+ break;
+ default:
+ dev_err(component->dev, "Rate %d is not supported\n",
+ params_rate(params));
+ return -EINVAL;
+ }
+
+ /* set sampling frequency */
+ regmap_write(rt1318->regmap,
+ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
+ sampling_rate);
+
+ return 0;
+}
+
+static int rt1318_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_component *component = dai->component;
+ struct rt1318_sdw_priv *rt1318 =
+ snd_soc_component_get_drvdata(component);
+ struct sdw_stream_data *stream =
+ snd_soc_dai_get_dma_data(dai, substream);
+
+ if (!rt1318->sdw_slave)
+ return -EINVAL;
+
+ sdw_stream_remove_slave(rt1318->sdw_slave, stream->sdw_stream);
+ return 0;
+}
+
+/*
+ * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
+ * port_prep are not defined for now
+ */
+static const struct sdw_slave_ops rt1318_slave_ops = {
+ .read_prop = rt1318_read_prop,
+ .update_status = rt1318_update_status,
+};
+
+static int rt1318_sdw_component_probe(struct snd_soc_component *component)
+{
+ int ret;
+ struct rt1318_sdw_priv *rt1318 = snd_soc_component_get_drvdata(component);
+
+ rt1318->component = component;
+
+ ret = pm_runtime_resume(component->dev);
+ dev_dbg(&rt1318->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret);
+ if (ret < 0 && ret != -EACCES)
+ return ret;
+
+ return 0;
+}
+
+static const struct snd_soc_component_driver soc_component_sdw_rt1318 = {
+ .probe = rt1318_sdw_component_probe,
+ .controls = rt1318_snd_controls,
+ .num_controls = ARRAY_SIZE(rt1318_snd_controls),
+ .dapm_widgets = rt1318_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(rt1318_dapm_widgets),
+ .dapm_routes = rt1318_dapm_routes,
+ .num_dapm_routes = ARRAY_SIZE(rt1318_dapm_routes),
+ .endianness = 1,
+};
+
+static const struct snd_soc_dai_ops rt1318_aif_dai_ops = {
+ .hw_params = rt1318_sdw_hw_params,
+ .hw_free = rt1318_sdw_pcm_hw_free,
+ .set_stream = rt1318_set_sdw_stream,
+ .shutdown = rt1318_sdw_shutdown,
+};
+
+#define RT1318_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
+ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
+#define RT1318_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_driver rt1318_sdw_dai[] = {
+ {
+ .name = "rt1318-aif",
+ .playback = {
+ .stream_name = "DP1 Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT1318_STEREO_RATES,
+ .formats = RT1318_FORMATS,
+ },
+ .capture = {
+ .stream_name = "DP2 Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT1318_STEREO_RATES,
+ .formats = RT1318_FORMATS,
+ },
+ .ops = &rt1318_aif_dai_ops,
+ },
+};
+
+static int rt1318_sdw_init(struct device *dev, struct regmap *regmap,
+ struct sdw_slave *slave)
+{
+ struct rt1318_sdw_priv *rt1318;
+ int ret;
+
+ rt1318 = devm_kzalloc(dev, sizeof(*rt1318), GFP_KERNEL);
+ if (!rt1318)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, rt1318);
+ rt1318->sdw_slave = slave;
+ rt1318->regmap = regmap;
+
+ /*
+ * Mark hw_init to false
+ * HW init will be performed when device reports present
+ */
+ rt1318->hw_init = false;
+ rt1318->first_hw_init = false;
+
+ ret = devm_snd_soc_register_component(dev,
+ &soc_component_sdw_rt1318,
+ rt1318_sdw_dai,
+ ARRAY_SIZE(rt1318_sdw_dai));
+
+ dev_dbg(&slave->dev, "%s\n", __func__);
+
+ return ret;
+}
+
+static int rt1318_sdw_probe(struct sdw_slave *slave,
+ const struct sdw_device_id *id)
+{
+ struct regmap *regmap;
+
+ /* Regmap Initialization */
+ regmap = devm_regmap_init_sdw(slave, &rt1318_sdw_regmap);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ return rt1318_sdw_init(&slave->dev, regmap, slave);
+}
+
+static int rt1318_sdw_remove(struct sdw_slave *slave)
+{
+ struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(&slave->dev);
+
+ if (rt1318->first_hw_init)
+ pm_runtime_disable(&slave->dev);
+
+ return 0;
+}
+
+static const struct sdw_device_id rt1318_id[] = {
+ SDW_SLAVE_ENTRY_EXT(0x025d, 0x1318, 0x3, 0x1, 0),
+ {},
+};
+MODULE_DEVICE_TABLE(sdw, rt1318_id);
+
+static int __maybe_unused rt1318_dev_suspend(struct device *dev)
+{
+ struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev);
+
+ if (!rt1318->hw_init)
+ return 0;
+
+ regcache_cache_only(rt1318->regmap, true);
+ return 0;
+}
+
+#define RT1318_PROBE_TIMEOUT 5000
+
+static int __maybe_unused rt1318_dev_resume(struct device *dev)
+{
+ struct sdw_slave *slave = dev_to_sdw_dev(dev);
+ struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev);
+ unsigned long time;
+
+ if (!rt1318->first_hw_init)
+ return 0;
+
+ if (!slave->unattach_request)
+ goto regmap_sync;
+
+ time = wait_for_completion_timeout(&slave->initialization_complete,
+ msecs_to_jiffies(RT1318_PROBE_TIMEOUT));
+ if (!time) {
+ dev_err(&slave->dev, "Initialization not complete, timed out\n");
+ return -ETIMEDOUT;
+ }
+
+regmap_sync:
+ slave->unattach_request = 0;
+ regcache_cache_only(rt1318->regmap, false);
+ regcache_sync(rt1318->regmap);
+
+ return 0;
+}
+
+static const struct dev_pm_ops rt1318_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(rt1318_dev_suspend, rt1318_dev_resume)
+ SET_RUNTIME_PM_OPS(rt1318_dev_suspend, rt1318_dev_resume, NULL)
+};
+
+static struct sdw_driver rt1318_sdw_driver = {
+ .driver = {
+ .name = "rt1318-sdca",
+ .owner = THIS_MODULE,
+ .pm = &rt1318_pm,
+ },
+ .probe = rt1318_sdw_probe,
+ .remove = rt1318_sdw_remove,
+ .ops = &rt1318_slave_ops,
+ .id_table = rt1318_id,
+};
+module_sdw_driver(rt1318_sdw_driver);
+
+MODULE_DESCRIPTION("ASoC RT1318 driver SDCA SDW");
+MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/rt1318-sdw.h b/sound/soc/codecs/rt1318-sdw.h
new file mode 100644
index 000000000000..4d7ac9c4bd8d
--- /dev/null
+++ b/sound/soc/codecs/rt1318-sdw.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * rt1318-sdw.h -- RT1318 SDCA ALSA SoC audio driver header
+ *
+ * Copyright(c) 2022 Realtek Semiconductor Corp.
+ */
+
+#ifndef __RT1318_SDW_H__
+#define __RT1318_SDW_H__
+
+#include <linux/regmap.h>
+#include <linux/soundwire/sdw.h>
+#include <linux/soundwire/sdw_type.h>
+#include <linux/soundwire/sdw_registers.h>
+#include <sound/soc.h>
+
+/* imp-defined registers */
+#define RT1318_SAPU_SM 0x3203
+
+#define R1318_TCON 0xc203
+#define R1318_TCON_RELATED_1 0xc206
+
+#define R1318_SPK_TEMPERATRUE_PROTECTION_0 0xdb00
+#define R1318_SPK_TEMPERATRUE_PROTECTION_L_4 0xdb08
+#define R1318_SPK_TEMPERATRUE_PROTECTION_R_4 0xdd08
+
+#define R1318_SPK_TEMPERATRUE_PROTECTION_L_6 0xdb12
+#define R1318_SPK_TEMPERATRUE_PROTECTION_R_6 0xdd12
+
+#define RT1318_INIT_RECIPROCAL_REG_L_24 0xdbb5
+#define RT1318_INIT_RECIPROCAL_REG_L_23_16 0xdbb6
+#define RT1318_INIT_RECIPROCAL_REG_L_15_8 0xdbb7
+#define RT1318_INIT_RECIPROCAL_REG_L_7_0 0xdbb8
+#define RT1318_INIT_RECIPROCAL_REG_R_24 0xddb5
+#define RT1318_INIT_RECIPROCAL_REG_R_23_16 0xddb6
+#define RT1318_INIT_RECIPROCAL_REG_R_15_8 0xddb7
+#define RT1318_INIT_RECIPROCAL_REG_R_7_0 0xddb8
+
+#define RT1318_INIT_R0_RECIPROCAL_SYN_L_24 0xdbc5
+#define RT1318_INIT_R0_RECIPROCAL_SYN_L_23_16 0xdbc6
+#define RT1318_INIT_R0_RECIPROCAL_SYN_L_15_8 0xdbc7
+#define RT1318_INIT_R0_RECIPROCAL_SYN_L_7_0 0xdbc8
+#define RT1318_INIT_R0_RECIPROCAL_SYN_R_24 0xddc5
+#define RT1318_INIT_R0_RECIPROCAL_SYN_R_23_16 0xddc6
+#define RT1318_INIT_R0_RECIPROCAL_SYN_R_15_8 0xddc7
+#define RT1318_INIT_R0_RECIPROCAL_SYN_R_7_0 0xddc8
+
+#define RT1318_R0_COMPARE_FLAG_L 0xdb35
+#define RT1318_R0_COMPARE_FLAG_R 0xdd35
+
+#define RT1318_STP_INITIAL_RS_TEMP_H 0xdd93
+#define RT1318_STP_INITIAL_RS_TEMP_L 0xdd94
+
+/* RT1318 SDCA Control - function number */
+#define FUNC_NUM_SMART_AMP 0x04
+
+/* RT1318 SDCA entity */
+#define RT1318_SDCA_ENT_PDE23 0x31
+#define RT1318_SDCA_ENT_XU24 0x24
+#define RT1318_SDCA_ENT_FU21 0x03
+#define RT1318_SDCA_ENT_UDMPU21 0x02
+#define RT1318_SDCA_ENT_CS21 0x21
+#define RT1318_SDCA_ENT_SAPU 0x29
+
+/* RT1318 SDCA control */
+#define RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10
+#define RT1318_SDCA_CTL_REQ_POWER_STATE 0x01
+#define RT1318_SDCA_CTL_FU_MUTE 0x01
+#define RT1318_SDCA_CTL_FU_VOLUME 0x02
+#define RT1318_SDCA_CTL_UDMPU_CLUSTER 0x10
+#define RT1318_SDCA_CTL_SAPU_PROTECTION_MODE 0x10
+#define RT1318_SDCA_CTL_SAPU_PROTECTION_STATUS 0x11
+
+/* RT1318 SDCA channel */
+#define CH_L 0x01
+#define CH_R 0x02
+
+/* sample frequency index */
+#define RT1318_SDCA_RATE_16000HZ 0x04
+#define RT1318_SDCA_RATE_32000HZ 0x07
+#define RT1318_SDCA_RATE_44100HZ 0x08
+#define RT1318_SDCA_RATE_48000HZ 0x09
+#define RT1318_SDCA_RATE_96000HZ 0x0b
+#define RT1318_SDCA_RATE_192000HZ 0x0d
+
+
+struct rt1318_sdw_priv {
+ struct snd_soc_component *component;
+ struct regmap *regmap;
+ struct sdw_slave *sdw_slave;
+ enum sdw_slave_status status;
+ struct sdw_bus_params params;
+ bool hw_init;
+ bool first_hw_init;
+};
+
+struct sdw_stream_data {
+ struct sdw_stream_runtime *sdw_stream;
+};
+
+#endif /* __RT1318_SDW_H__ */
diff --git a/sound/soc/codecs/rt711-sdca-sdw.c b/sound/soc/codecs/rt711-sdca-sdw.c
index 88a8392a58ed..e23cec4c457d 100644
--- a/sound/soc/codecs/rt711-sdca-sdw.c
+++ b/sound/soc/codecs/rt711-sdca-sdw.c
@@ -338,7 +338,7 @@ io_error:
return ret;
}
-static struct sdw_slave_ops rt711_sdca_slave_ops = {
+static const struct sdw_slave_ops rt711_sdca_slave_ops = {
.read_prop = rt711_sdca_read_prop,
.interrupt_callback = rt711_sdca_interrupt_callback,
.update_status = rt711_sdca_update_status,
diff --git a/sound/soc/codecs/rt715-sdca-sdw.c b/sound/soc/codecs/rt715-sdca-sdw.c
index c54ecf3e6987..38a82e4e2f95 100644
--- a/sound/soc/codecs/rt715-sdca-sdw.c
+++ b/sound/soc/codecs/rt715-sdca-sdw.c
@@ -172,7 +172,7 @@ static int rt715_sdca_read_prop(struct sdw_slave *slave)
return 0;
}
-static struct sdw_slave_ops rt715_sdca_slave_ops = {
+static const struct sdw_slave_ops rt715_sdca_slave_ops = {
.read_prop = rt715_sdca_read_prop,
.update_status = rt715_sdca_update_status,
};
diff --git a/sound/soc/codecs/wcd938x-sdw.c b/sound/soc/codecs/wcd938x-sdw.c
index 1bf3c06a2b62..402286dfaea4 100644
--- a/sound/soc/codecs/wcd938x-sdw.c
+++ b/sound/soc/codecs/wcd938x-sdw.c
@@ -161,6 +161,14 @@ EXPORT_SYMBOL_GPL(wcd938x_sdw_set_sdw_stream);
static int wcd9380_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
+ struct wcd938x_sdw_priv *wcd = dev_get_drvdata(&slave->dev);
+
+ if (wcd->regmap && (status == SDW_SLAVE_ATTACHED)) {
+ /* Write out any cached changes that happened between probe and attach */
+ regcache_cache_only(wcd->regmap, false);
+ return regcache_sync(wcd->regmap);
+ }
+
return 0;
}
@@ -177,21 +185,1015 @@ static int wcd9380_interrupt_callback(struct sdw_slave *slave,
{
struct wcd938x_sdw_priv *wcd = dev_get_drvdata(&slave->dev);
struct irq_domain *slave_irq = wcd->slave_irq;
- struct regmap *regmap = dev_get_regmap(&slave->dev, NULL);
u32 sts1, sts2, sts3;
do {
handle_nested_irq(irq_find_mapping(slave_irq, 0));
- regmap_read(regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
- regmap_read(regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
- regmap_read(regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
+ regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
+ regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
+ regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
} while (sts1 || sts2 || sts3);
return IRQ_HANDLED;
}
-static struct sdw_slave_ops wcd9380_slave_ops = {
+static const struct reg_default wcd938x_defaults[] = {
+ {WCD938X_ANA_PAGE_REGISTER, 0x00},
+ {WCD938X_ANA_BIAS, 0x00},
+ {WCD938X_ANA_RX_SUPPLIES, 0x00},
+ {WCD938X_ANA_HPH, 0x0C},
+ {WCD938X_ANA_EAR, 0x00},
+ {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02},
+ {WCD938X_ANA_TX_CH1, 0x20},
+ {WCD938X_ANA_TX_CH2, 0x00},
+ {WCD938X_ANA_TX_CH3, 0x20},
+ {WCD938X_ANA_TX_CH4, 0x00},
+ {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00},
+ {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00},
+ {WCD938X_ANA_MBHC_MECH, 0x39},
+ {WCD938X_ANA_MBHC_ELECT, 0x08},
+ {WCD938X_ANA_MBHC_ZDET, 0x00},
+ {WCD938X_ANA_MBHC_RESULT_1, 0x00},
+ {WCD938X_ANA_MBHC_RESULT_2, 0x00},
+ {WCD938X_ANA_MBHC_RESULT_3, 0x00},
+ {WCD938X_ANA_MBHC_BTN0, 0x00},
+ {WCD938X_ANA_MBHC_BTN1, 0x10},
+ {WCD938X_ANA_MBHC_BTN2, 0x20},
+ {WCD938X_ANA_MBHC_BTN3, 0x30},
+ {WCD938X_ANA_MBHC_BTN4, 0x40},
+ {WCD938X_ANA_MBHC_BTN5, 0x50},
+ {WCD938X_ANA_MBHC_BTN6, 0x60},
+ {WCD938X_ANA_MBHC_BTN7, 0x70},
+ {WCD938X_ANA_MICB1, 0x10},
+ {WCD938X_ANA_MICB2, 0x10},
+ {WCD938X_ANA_MICB2_RAMP, 0x00},
+ {WCD938X_ANA_MICB3, 0x10},
+ {WCD938X_ANA_MICB4, 0x10},
+ {WCD938X_BIAS_CTL, 0x2A},
+ {WCD938X_BIAS_VBG_FINE_ADJ, 0x55},
+ {WCD938X_LDOL_VDDCX_ADJUST, 0x01},
+ {WCD938X_LDOL_DISABLE_LDOL, 0x00},
+ {WCD938X_MBHC_CTL_CLK, 0x00},
+ {WCD938X_MBHC_CTL_ANA, 0x00},
+ {WCD938X_MBHC_CTL_SPARE_1, 0x00},
+ {WCD938X_MBHC_CTL_SPARE_2, 0x00},
+ {WCD938X_MBHC_CTL_BCS, 0x00},
+ {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00},
+ {WCD938X_MBHC_TEST_CTL, 0x00},
+ {WCD938X_LDOH_MODE, 0x2B},
+ {WCD938X_LDOH_BIAS, 0x68},
+ {WCD938X_LDOH_STB_LOADS, 0x00},
+ {WCD938X_LDOH_SLOWRAMP, 0x50},
+ {WCD938X_MICB1_TEST_CTL_1, 0x1A},
+ {WCD938X_MICB1_TEST_CTL_2, 0x00},
+ {WCD938X_MICB1_TEST_CTL_3, 0xA4},
+ {WCD938X_MICB2_TEST_CTL_1, 0x1A},
+ {WCD938X_MICB2_TEST_CTL_2, 0x00},
+ {WCD938X_MICB2_TEST_CTL_3, 0x24},
+ {WCD938X_MICB3_TEST_CTL_1, 0x1A},
+ {WCD938X_MICB3_TEST_CTL_2, 0x00},
+ {WCD938X_MICB3_TEST_CTL_3, 0xA4},
+ {WCD938X_MICB4_TEST_CTL_1, 0x1A},
+ {WCD938X_MICB4_TEST_CTL_2, 0x00},
+ {WCD938X_MICB4_TEST_CTL_3, 0xA4},
+ {WCD938X_TX_COM_ADC_VCM, 0x39},
+ {WCD938X_TX_COM_BIAS_ATEST, 0xE0},
+ {WCD938X_TX_COM_SPARE1, 0x00},
+ {WCD938X_TX_COM_SPARE2, 0x00},
+ {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22},
+ {WCD938X_TX_COM_TXFE_DIV_START, 0x00},
+ {WCD938X_TX_COM_SPARE3, 0x00},
+ {WCD938X_TX_COM_SPARE4, 0x00},
+ {WCD938X_TX_1_2_TEST_EN, 0xCC},
+ {WCD938X_TX_1_2_ADC_IB, 0xE9},
+ {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A},
+ {WCD938X_TX_1_2_TEST_CTL, 0x38},
+ {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF},
+ {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00},
+ {WCD938X_TX_1_2_SAR2_ERR, 0x00},
+ {WCD938X_TX_1_2_SAR1_ERR, 0x00},
+ {WCD938X_TX_3_4_TEST_EN, 0xCC},
+ {WCD938X_TX_3_4_ADC_IB, 0xE9},
+ {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A},
+ {WCD938X_TX_3_4_TEST_CTL, 0x38},
+ {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF},
+ {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00},
+ {WCD938X_TX_3_4_SAR4_ERR, 0x00},
+ {WCD938X_TX_3_4_SAR3_ERR, 0x00},
+ {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB},
+ {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00},
+ {WCD938X_TX_3_4_SPARE1, 0x00},
+ {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB},
+ {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00},
+ {WCD938X_TX_3_4_SPARE2, 0x00},
+ {WCD938X_CLASSH_MODE_1, 0x40},
+ {WCD938X_CLASSH_MODE_2, 0x3A},
+ {WCD938X_CLASSH_MODE_3, 0x00},
+ {WCD938X_CLASSH_CTRL_VCL_1, 0x70},
+ {WCD938X_CLASSH_CTRL_VCL_2, 0x82},
+ {WCD938X_CLASSH_CTRL_CCL_1, 0x31},
+ {WCD938X_CLASSH_CTRL_CCL_2, 0x80},
+ {WCD938X_CLASSH_CTRL_CCL_3, 0x80},
+ {WCD938X_CLASSH_CTRL_CCL_4, 0x51},
+ {WCD938X_CLASSH_CTRL_CCL_5, 0x00},
+ {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00},
+ {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77},
+ {WCD938X_CLASSH_SPARE, 0x00},
+ {WCD938X_FLYBACK_EN, 0x4E},
+ {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B},
+ {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45},
+ {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74},
+ {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F},
+ {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83},
+ {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98},
+ {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9},
+ {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68},
+ {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64},
+ {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED},
+ {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0},
+ {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6},
+ {WCD938X_FLYBACK_CTRL_1, 0x65},
+ {WCD938X_FLYBACK_TEST_CTL, 0x00},
+ {WCD938X_RX_AUX_SW_CTL, 0x00},
+ {WCD938X_RX_PA_AUX_IN_CONN, 0x01},
+ {WCD938X_RX_TIMER_DIV, 0x32},
+ {WCD938X_RX_OCP_CTL, 0x1F},
+ {WCD938X_RX_OCP_COUNT, 0x77},
+ {WCD938X_RX_BIAS_EAR_DAC, 0xA0},
+ {WCD938X_RX_BIAS_EAR_AMP, 0xAA},
+ {WCD938X_RX_BIAS_HPH_LDO, 0xA9},
+ {WCD938X_RX_BIAS_HPH_PA, 0xAA},
+ {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A},
+ {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88},
+ {WCD938X_RX_BIAS_HPH_CNP1, 0x82},
+ {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82},
+ {WCD938X_RX_BIAS_AUX_DAC, 0xA0},
+ {WCD938X_RX_BIAS_AUX_AMP, 0xAA},
+ {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50},
+ {WCD938X_RX_BIAS_MISC, 0x00},
+ {WCD938X_RX_BIAS_BUCK_RST, 0x08},
+ {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44},
+ {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40},
+ {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA},
+ {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14},
+ {WCD938X_HPH_L_STATUS, 0x04},
+ {WCD938X_HPH_R_STATUS, 0x04},
+ {WCD938X_HPH_CNP_EN, 0x80},
+ {WCD938X_HPH_CNP_WG_CTL, 0x9A},
+ {WCD938X_HPH_CNP_WG_TIME, 0x14},
+ {WCD938X_HPH_OCP_CTL, 0x28},
+ {WCD938X_HPH_AUTO_CHOP, 0x16},
+ {WCD938X_HPH_CHOP_CTL, 0x83},
+ {WCD938X_HPH_PA_CTL1, 0x46},
+ {WCD938X_HPH_PA_CTL2, 0x50},
+ {WCD938X_HPH_L_EN, 0x80},
+ {WCD938X_HPH_L_TEST, 0xE0},
+ {WCD938X_HPH_L_ATEST, 0x50},
+ {WCD938X_HPH_R_EN, 0x80},
+ {WCD938X_HPH_R_TEST, 0xE0},
+ {WCD938X_HPH_R_ATEST, 0x54},
+ {WCD938X_HPH_RDAC_CLK_CTL1, 0x99},
+ {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B},
+ {WCD938X_HPH_RDAC_LDO_CTL, 0x33},
+ {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00},
+ {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68},
+ {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E},
+ {WCD938X_HPH_L_DAC_CTL, 0x20},
+ {WCD938X_HPH_R_DAC_CTL, 0x20},
+ {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55},
+ {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19},
+ {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0},
+ {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00},
+ {WCD938X_EAR_EAR_EN_REG, 0x22},
+ {WCD938X_EAR_EAR_PA_CON, 0x44},
+ {WCD938X_EAR_EAR_SP_CON, 0xDB},
+ {WCD938X_EAR_EAR_DAC_CON, 0x80},
+ {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2},
+ {WCD938X_EAR_TEST_CTL, 0x00},
+ {WCD938X_EAR_STATUS_REG_1, 0x00},
+ {WCD938X_EAR_STATUS_REG_2, 0x08},
+ {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00},
+ {WCD938X_HPH_NEW_ANA_HPH2, 0x00},
+ {WCD938X_HPH_NEW_ANA_HPH3, 0x00},
+ {WCD938X_SLEEP_CTL, 0x16},
+ {WCD938X_SLEEP_WATCHDOG_CTL, 0x00},
+ {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00},
+ {WCD938X_MBHC_NEW_CTL_1, 0x02},
+ {WCD938X_MBHC_NEW_CTL_2, 0x05},
+ {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9},
+ {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F},
+ {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00},
+ {WCD938X_MBHC_NEW_FSM_STATUS, 0x00},
+ {WCD938X_MBHC_NEW_ADC_RESULT, 0x00},
+ {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00},
+ {WCD938X_AUX_AUXPA, 0x00},
+ {WCD938X_LDORXTX_MODE, 0x0C},
+ {WCD938X_LDORXTX_CONFIG, 0x10},
+ {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00},
+ {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00},
+ {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40},
+ {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81},
+ {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10},
+ {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00},
+ {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81},
+ {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22},
+ {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00},
+ {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00},
+ {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE},
+ {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02},
+ {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E},
+ {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54},
+ {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00},
+ {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00},
+ {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90},
+ {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90},
+ {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62},
+ {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01},
+ {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11},
+ {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57},
+ {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01},
+ {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00},
+ {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00},
+ {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8},
+ {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42},
+ {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22},
+ {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00},
+ {WCD938X_AUX_INT_EN_REG, 0x00},
+ {WCD938X_AUX_INT_PA_CTRL, 0x06},
+ {WCD938X_AUX_INT_SP_CTRL, 0xD2},
+ {WCD938X_AUX_INT_DAC_CTRL, 0x80},
+ {WCD938X_AUX_INT_CLK_CTRL, 0x50},
+ {WCD938X_AUX_INT_TEST_CTRL, 0x00},
+ {WCD938X_AUX_INT_STATUS_REG, 0x00},
+ {WCD938X_AUX_INT_MISC, 0x00},
+ {WCD938X_LDORXTX_INT_BIAS, 0x6E},
+ {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50},
+ {WCD938X_LDORXTX_INT_TEST0, 0x1C},
+ {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF},
+ {WCD938X_LDORXTX_INT_TEST1, 0x1F},
+ {WCD938X_LDORXTX_INT_STATUS, 0x00},
+ {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A},
+ {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A},
+ {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02},
+ {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60},
+ {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF},
+ {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F},
+ {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F},
+ {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F},
+ {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F},
+ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7},
+ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8},
+ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6},
+ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5},
+ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA},
+ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05},
+ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5},
+ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13},
+ {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88},
+ {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42},
+ {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF},
+ {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64},
+ {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64},
+ {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77},
+ {WCD938X_DIGITAL_PAGE_REGISTER, 0x00},
+ {WCD938X_DIGITAL_CHIP_ID0, 0x00},
+ {WCD938X_DIGITAL_CHIP_ID1, 0x00},
+ {WCD938X_DIGITAL_CHIP_ID2, 0x0D},
+ {WCD938X_DIGITAL_CHIP_ID3, 0x01},
+ {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00},
+ {WCD938X_DIGITAL_CDC_RST_CTL, 0x03},
+ {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00},
+ {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00},
+ {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0},
+ {WCD938X_DIGITAL_SWR_RST_EN, 0x00},
+ {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55},
+ {WCD938X_DIGITAL_CDC_RX_RST, 0x00},
+ {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC},
+ {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC},
+ {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC},
+ {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00},
+ {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00},
+ {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00},
+ {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87},
+ {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2},
+ {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62},
+ {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55},
+ {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9},
+ {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D},
+ {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E},
+ {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01},
+ {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00},
+ {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC},
+ {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01},
+ {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00},
+ {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00},
+ {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00},
+ {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00},
+ {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00},
+ {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68},
+ {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68},
+ {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68},
+ {WCD938X_DIGITAL_CDC_TX_RST, 0x00},
+ {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01},
+ {WCD938X_DIGITAL_CDC_RST, 0x00},
+ {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F},
+ {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04},
+ {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01},
+ {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01},
+ {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01},
+ {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01},
+ {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00},
+ {WCD938X_DIGITAL_EFUSE_CTL, 0x2B},
+ {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11},
+ {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11},
+ {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00},
+ {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00},
+ {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00},
+ {WCD938X_DIGITAL_INTR_MODE, 0x00},
+ {WCD938X_DIGITAL_INTR_MASK_0, 0xFF},
+ {WCD938X_DIGITAL_INTR_MASK_1, 0xFF},
+ {WCD938X_DIGITAL_INTR_MASK_2, 0x3F},
+ {WCD938X_DIGITAL_INTR_STATUS_0, 0x00},
+ {WCD938X_DIGITAL_INTR_STATUS_1, 0x00},
+ {WCD938X_DIGITAL_INTR_STATUS_2, 0x00},
+ {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00},
+ {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00},
+ {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00},
+ {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00},
+ {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00},
+ {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00},
+ {WCD938X_DIGITAL_INTR_SET_0, 0x00},
+ {WCD938X_DIGITAL_INTR_SET_1, 0x00},
+ {WCD938X_DIGITAL_INTR_SET_2, 0x00},
+ {WCD938X_DIGITAL_INTR_TEST_0, 0x00},
+ {WCD938X_DIGITAL_INTR_TEST_1, 0x00},
+ {WCD938X_DIGITAL_INTR_TEST_2, 0x00},
+ {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00},
+ {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00},
+ {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00},
+ {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00},
+ {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00},
+ {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00},
+ {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40},
+ {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40},
+ {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00},
+ {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00},
+ {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00},
+ {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00},
+ {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00},
+ {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F},
+ {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06},
+ {WCD938X_DIGITAL_I2C_CTL, 0x00},
+ {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00},
+ {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00},
+ {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00},
+ {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00},
+ {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00},
+ {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1},
+ {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1},
+ {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1},
+ {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1},
+ {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1},
+ {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00},
+ {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00},
+ {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00},
+ {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00},
+ {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00},
+ {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F},
+ {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80},
+ {WCD938X_DIGITAL_GPIO_MODE, 0x00},
+ {WCD938X_DIGITAL_PIN_CTL_OE, 0x00},
+ {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00},
+ {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00},
+ {WCD938X_DIGITAL_PIN_STATUS_0, 0x00},
+ {WCD938X_DIGITAL_PIN_STATUS_1, 0x00},
+ {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00},
+ {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00},
+ {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00},
+ {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48},
+ {WCD938X_DIGITAL_SSP_DBG, 0x00},
+ {WCD938X_DIGITAL_MODE_STATUS_0, 0x00},
+ {WCD938X_DIGITAL_MODE_STATUS_1, 0x00},
+ {WCD938X_DIGITAL_SPARE_0, 0x00},
+ {WCD938X_DIGITAL_SPARE_1, 0x00},
+ {WCD938X_DIGITAL_SPARE_2, 0x00},
+ {WCD938X_DIGITAL_EFUSE_REG_0, 0x00},
+ {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF},
+ {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E},
+ {WCD938X_DIGITAL_EFUSE_REG_21, 0x00},
+ {WCD938X_DIGITAL_EFUSE_REG_22, 0x00},
+ {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8},
+ {WCD938X_DIGITAL_EFUSE_REG_24, 0x16},
+ {WCD938X_DIGITAL_EFUSE_REG_25, 0x00},
+ {WCD938X_DIGITAL_EFUSE_REG_26, 0x00},
+ {WCD938X_DIGITAL_EFUSE_REG_27, 0x00},
+ {WCD938X_DIGITAL_EFUSE_REG_28, 0x00},
+ {WCD938X_DIGITAL_EFUSE_REG_29, 0x00},
+ {WCD938X_DIGITAL_EFUSE_REG_30, 0x00},
+ {WCD938X_DIGITAL_EFUSE_REG_31, 0x00},
+ {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88},
+ {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88},
+ {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88},
+ {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88},
+ {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88},
+ {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55},
+ {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55},
+ {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55},
+ {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01},
+};
+
+static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case WCD938X_ANA_PAGE_REGISTER:
+ case WCD938X_ANA_BIAS:
+ case WCD938X_ANA_RX_SUPPLIES:
+ case WCD938X_ANA_HPH:
+ case WCD938X_ANA_EAR:
+ case WCD938X_ANA_EAR_COMPANDER_CTL:
+ case WCD938X_ANA_TX_CH1:
+ case WCD938X_ANA_TX_CH2:
+ case WCD938X_ANA_TX_CH3:
+ case WCD938X_ANA_TX_CH4:
+ case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC:
+ case WCD938X_ANA_MICB3_DSP_EN_LOGIC:
+ case WCD938X_ANA_MBHC_MECH:
+ case WCD938X_ANA_MBHC_ELECT:
+ case WCD938X_ANA_MBHC_ZDET:
+ case WCD938X_ANA_MBHC_BTN0:
+ case WCD938X_ANA_MBHC_BTN1:
+ case WCD938X_ANA_MBHC_BTN2:
+ case WCD938X_ANA_MBHC_BTN3:
+ case WCD938X_ANA_MBHC_BTN4:
+ case WCD938X_ANA_MBHC_BTN5:
+ case WCD938X_ANA_MBHC_BTN6:
+ case WCD938X_ANA_MBHC_BTN7:
+ case WCD938X_ANA_MICB1:
+ case WCD938X_ANA_MICB2:
+ case WCD938X_ANA_MICB2_RAMP:
+ case WCD938X_ANA_MICB3:
+ case WCD938X_ANA_MICB4:
+ case WCD938X_BIAS_CTL:
+ case WCD938X_BIAS_VBG_FINE_ADJ:
+ case WCD938X_LDOL_VDDCX_ADJUST:
+ case WCD938X_LDOL_DISABLE_LDOL:
+ case WCD938X_MBHC_CTL_CLK:
+ case WCD938X_MBHC_CTL_ANA:
+ case WCD938X_MBHC_CTL_SPARE_1:
+ case WCD938X_MBHC_CTL_SPARE_2:
+ case WCD938X_MBHC_CTL_BCS:
+ case WCD938X_MBHC_TEST_CTL:
+ case WCD938X_LDOH_MODE:
+ case WCD938X_LDOH_BIAS:
+ case WCD938X_LDOH_STB_LOADS:
+ case WCD938X_LDOH_SLOWRAMP:
+ case WCD938X_MICB1_TEST_CTL_1:
+ case WCD938X_MICB1_TEST_CTL_2:
+ case WCD938X_MICB1_TEST_CTL_3:
+ case WCD938X_MICB2_TEST_CTL_1:
+ case WCD938X_MICB2_TEST_CTL_2:
+ case WCD938X_MICB2_TEST_CTL_3:
+ case WCD938X_MICB3_TEST_CTL_1:
+ case WCD938X_MICB3_TEST_CTL_2:
+ case WCD938X_MICB3_TEST_CTL_3:
+ case WCD938X_MICB4_TEST_CTL_1:
+ case WCD938X_MICB4_TEST_CTL_2:
+ case WCD938X_MICB4_TEST_CTL_3:
+ case WCD938X_TX_COM_ADC_VCM:
+ case WCD938X_TX_COM_BIAS_ATEST:
+ case WCD938X_TX_COM_SPARE1:
+ case WCD938X_TX_COM_SPARE2:
+ case WCD938X_TX_COM_TXFE_DIV_CTL:
+ case WCD938X_TX_COM_TXFE_DIV_START:
+ case WCD938X_TX_COM_SPARE3:
+ case WCD938X_TX_COM_SPARE4:
+ case WCD938X_TX_1_2_TEST_EN:
+ case WCD938X_TX_1_2_ADC_IB:
+ case WCD938X_TX_1_2_ATEST_REFCTL:
+ case WCD938X_TX_1_2_TEST_CTL:
+ case WCD938X_TX_1_2_TEST_BLK_EN1:
+ case WCD938X_TX_1_2_TXFE1_CLKDIV:
+ case WCD938X_TX_3_4_TEST_EN:
+ case WCD938X_TX_3_4_ADC_IB:
+ case WCD938X_TX_3_4_ATEST_REFCTL:
+ case WCD938X_TX_3_4_TEST_CTL:
+ case WCD938X_TX_3_4_TEST_BLK_EN3:
+ case WCD938X_TX_3_4_TXFE3_CLKDIV:
+ case WCD938X_TX_3_4_TEST_BLK_EN2:
+ case WCD938X_TX_3_4_TXFE2_CLKDIV:
+ case WCD938X_TX_3_4_SPARE1:
+ case WCD938X_TX_3_4_TEST_BLK_EN4:
+ case WCD938X_TX_3_4_TXFE4_CLKDIV:
+ case WCD938X_TX_3_4_SPARE2:
+ case WCD938X_CLASSH_MODE_1:
+ case WCD938X_CLASSH_MODE_2:
+ case WCD938X_CLASSH_MODE_3:
+ case WCD938X_CLASSH_CTRL_VCL_1:
+ case WCD938X_CLASSH_CTRL_VCL_2:
+ case WCD938X_CLASSH_CTRL_CCL_1:
+ case WCD938X_CLASSH_CTRL_CCL_2:
+ case WCD938X_CLASSH_CTRL_CCL_3:
+ case WCD938X_CLASSH_CTRL_CCL_4:
+ case WCD938X_CLASSH_CTRL_CCL_5:
+ case WCD938X_CLASSH_BUCK_TMUX_A_D:
+ case WCD938X_CLASSH_BUCK_SW_DRV_CNTL:
+ case WCD938X_CLASSH_SPARE:
+ case WCD938X_FLYBACK_EN:
+ case WCD938X_FLYBACK_VNEG_CTRL_1:
+ case WCD938X_FLYBACK_VNEG_CTRL_2:
+ case WCD938X_FLYBACK_VNEG_CTRL_3:
+ case WCD938X_FLYBACK_VNEG_CTRL_4:
+ case WCD938X_FLYBACK_VNEG_CTRL_5:
+ case WCD938X_FLYBACK_VNEG_CTRL_6:
+ case WCD938X_FLYBACK_VNEG_CTRL_7:
+ case WCD938X_FLYBACK_VNEG_CTRL_8:
+ case WCD938X_FLYBACK_VNEG_CTRL_9:
+ case WCD938X_FLYBACK_VNEGDAC_CTRL_1:
+ case WCD938X_FLYBACK_VNEGDAC_CTRL_2:
+ case WCD938X_FLYBACK_VNEGDAC_CTRL_3:
+ case WCD938X_FLYBACK_CTRL_1:
+ case WCD938X_FLYBACK_TEST_CTL:
+ case WCD938X_RX_AUX_SW_CTL:
+ case WCD938X_RX_PA_AUX_IN_CONN:
+ case WCD938X_RX_TIMER_DIV:
+ case WCD938X_RX_OCP_CTL:
+ case WCD938X_RX_OCP_COUNT:
+ case WCD938X_RX_BIAS_EAR_DAC:
+ case WCD938X_RX_BIAS_EAR_AMP:
+ case WCD938X_RX_BIAS_HPH_LDO:
+ case WCD938X_RX_BIAS_HPH_PA:
+ case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2:
+ case WCD938X_RX_BIAS_HPH_RDAC_LDO:
+ case WCD938X_RX_BIAS_HPH_CNP1:
+ case WCD938X_RX_BIAS_HPH_LOWPOWER:
+ case WCD938X_RX_BIAS_AUX_DAC:
+ case WCD938X_RX_BIAS_AUX_AMP:
+ case WCD938X_RX_BIAS_VNEGDAC_BLEEDER:
+ case WCD938X_RX_BIAS_MISC:
+ case WCD938X_RX_BIAS_BUCK_RST:
+ case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP:
+ case WCD938X_RX_BIAS_FLYB_ERRAMP:
+ case WCD938X_RX_BIAS_FLYB_BUFF:
+ case WCD938X_RX_BIAS_FLYB_MID_RST:
+ case WCD938X_HPH_CNP_EN:
+ case WCD938X_HPH_CNP_WG_CTL:
+ case WCD938X_HPH_CNP_WG_TIME:
+ case WCD938X_HPH_OCP_CTL:
+ case WCD938X_HPH_AUTO_CHOP:
+ case WCD938X_HPH_CHOP_CTL:
+ case WCD938X_HPH_PA_CTL1:
+ case WCD938X_HPH_PA_CTL2:
+ case WCD938X_HPH_L_EN:
+ case WCD938X_HPH_L_TEST:
+ case WCD938X_HPH_L_ATEST:
+ case WCD938X_HPH_R_EN:
+ case WCD938X_HPH_R_TEST:
+ case WCD938X_HPH_R_ATEST:
+ case WCD938X_HPH_RDAC_CLK_CTL1:
+ case WCD938X_HPH_RDAC_CLK_CTL2:
+ case WCD938X_HPH_RDAC_LDO_CTL:
+ case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL:
+ case WCD938X_HPH_REFBUFF_UHQA_CTL:
+ case WCD938X_HPH_REFBUFF_LP_CTL:
+ case WCD938X_HPH_L_DAC_CTL:
+ case WCD938X_HPH_R_DAC_CTL:
+ case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL:
+ case WCD938X_HPH_SURGE_HPHLR_SURGE_EN:
+ case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1:
+ case WCD938X_EAR_EAR_EN_REG:
+ case WCD938X_EAR_EAR_PA_CON:
+ case WCD938X_EAR_EAR_SP_CON:
+ case WCD938X_EAR_EAR_DAC_CON:
+ case WCD938X_EAR_EAR_CNP_FSM_CON:
+ case WCD938X_EAR_TEST_CTL:
+ case WCD938X_ANA_NEW_PAGE_REGISTER:
+ case WCD938X_HPH_NEW_ANA_HPH2:
+ case WCD938X_HPH_NEW_ANA_HPH3:
+ case WCD938X_SLEEP_CTL:
+ case WCD938X_SLEEP_WATCHDOG_CTL:
+ case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL:
+ case WCD938X_MBHC_NEW_CTL_1:
+ case WCD938X_MBHC_NEW_CTL_2:
+ case WCD938X_MBHC_NEW_PLUG_DETECT_CTL:
+ case WCD938X_MBHC_NEW_ZDET_ANA_CTL:
+ case WCD938X_MBHC_NEW_ZDET_RAMP_CTL:
+ case WCD938X_TX_NEW_AMIC_MUX_CFG:
+ case WCD938X_AUX_AUXPA:
+ case WCD938X_LDORXTX_MODE:
+ case WCD938X_LDORXTX_CONFIG:
+ case WCD938X_DIE_CRACK_DIE_CRK_DET_EN:
+ case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL:
+ case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L:
+ case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL:
+ case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL:
+ case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R:
+ case WCD938X_HPH_NEW_INT_PA_MISC1:
+ case WCD938X_HPH_NEW_INT_PA_MISC2:
+ case WCD938X_HPH_NEW_INT_PA_RDAC_MISC:
+ case WCD938X_HPH_NEW_INT_HPH_TIMER1:
+ case WCD938X_HPH_NEW_INT_HPH_TIMER2:
+ case WCD938X_HPH_NEW_INT_HPH_TIMER3:
+ case WCD938X_HPH_NEW_INT_HPH_TIMER4:
+ case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2:
+ case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3:
+ case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW:
+ case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW:
+ case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI:
+ case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP:
+ case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP:
+ case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL:
+ case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL:
+ case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT:
+ case WCD938X_MBHC_NEW_INT_SPARE_2:
+ case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON:
+ case WCD938X_EAR_INT_NEW_CNP_VCM_CON1:
+ case WCD938X_EAR_INT_NEW_CNP_VCM_CON2:
+ case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS:
+ case WCD938X_AUX_INT_EN_REG:
+ case WCD938X_AUX_INT_PA_CTRL:
+ case WCD938X_AUX_INT_SP_CTRL:
+ case WCD938X_AUX_INT_DAC_CTRL:
+ case WCD938X_AUX_INT_CLK_CTRL:
+ case WCD938X_AUX_INT_TEST_CTRL:
+ case WCD938X_AUX_INT_MISC:
+ case WCD938X_LDORXTX_INT_BIAS:
+ case WCD938X_LDORXTX_INT_STB_LOADS_DTEST:
+ case WCD938X_LDORXTX_INT_TEST0:
+ case WCD938X_LDORXTX_INT_STARTUP_TIMER:
+ case WCD938X_LDORXTX_INT_TEST1:
+ case WCD938X_SLEEP_INT_WATCHDOG_CTL_1:
+ case WCD938X_SLEEP_INT_WATCHDOG_CTL_2:
+ case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1:
+ case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2:
+ case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2:
+ case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1:
+ case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0:
+ case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M:
+ case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M:
+ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1:
+ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0:
+ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP:
+ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1:
+ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0:
+ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP:
+ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0:
+ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP:
+ case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1:
+ case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP:
+ case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2:
+ case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1:
+ case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0:
+ case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP:
+ case WCD938X_DIGITAL_PAGE_REGISTER:
+ case WCD938X_DIGITAL_SWR_TX_CLK_RATE:
+ case WCD938X_DIGITAL_CDC_RST_CTL:
+ case WCD938X_DIGITAL_TOP_CLK_CFG:
+ case WCD938X_DIGITAL_CDC_ANA_CLK_CTL:
+ case WCD938X_DIGITAL_CDC_DIG_CLK_CTL:
+ case WCD938X_DIGITAL_SWR_RST_EN:
+ case WCD938X_DIGITAL_CDC_PATH_MODE:
+ case WCD938X_DIGITAL_CDC_RX_RST:
+ case WCD938X_DIGITAL_CDC_RX0_CTL:
+ case WCD938X_DIGITAL_CDC_RX1_CTL:
+ case WCD938X_DIGITAL_CDC_RX2_CTL:
+ case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1:
+ case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3:
+ case WCD938X_DIGITAL_CDC_COMP_CTL_0:
+ case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_C_0:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_C_1:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_C_2:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_C_3:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_R1:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_R2:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_R3:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_R4:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_R5:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_R6:
+ case WCD938X_DIGITAL_CDC_HPH_DSM_R7:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_C_0:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_C_1:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_C_2:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_C_3:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_R1:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_R2:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_R3:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_R4:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_R5:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_R6:
+ case WCD938X_DIGITAL_CDC_AUX_DSM_R7:
+ case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0:
+ case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1:
+ case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0:
+ case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1:
+ case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2:
+ case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0:
+ case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1:
+ case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2:
+ case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL:
+ case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL:
+ case WCD938X_DIGITAL_CDC_EAR_PATH_CTL:
+ case WCD938X_DIGITAL_CDC_SWR_CLH:
+ case WCD938X_DIGITAL_SWR_CLH_BYP:
+ case WCD938X_DIGITAL_CDC_TX0_CTL:
+ case WCD938X_DIGITAL_CDC_TX1_CTL:
+ case WCD938X_DIGITAL_CDC_TX2_CTL:
+ case WCD938X_DIGITAL_CDC_TX_RST:
+ case WCD938X_DIGITAL_CDC_REQ_CTL:
+ case WCD938X_DIGITAL_CDC_RST:
+ case WCD938X_DIGITAL_CDC_AMIC_CTL:
+ case WCD938X_DIGITAL_CDC_DMIC_CTL:
+ case WCD938X_DIGITAL_CDC_DMIC1_CTL:
+ case WCD938X_DIGITAL_CDC_DMIC2_CTL:
+ case WCD938X_DIGITAL_CDC_DMIC3_CTL:
+ case WCD938X_DIGITAL_CDC_DMIC4_CTL:
+ case WCD938X_DIGITAL_EFUSE_PRG_CTL:
+ case WCD938X_DIGITAL_EFUSE_CTL:
+ case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2:
+ case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4:
+ case WCD938X_DIGITAL_PDM_WD_CTL0:
+ case WCD938X_DIGITAL_PDM_WD_CTL1:
+ case WCD938X_DIGITAL_PDM_WD_CTL2:
+ case WCD938X_DIGITAL_INTR_MODE:
+ case WCD938X_DIGITAL_INTR_MASK_0:
+ case WCD938X_DIGITAL_INTR_MASK_1:
+ case WCD938X_DIGITAL_INTR_MASK_2:
+ case WCD938X_DIGITAL_INTR_CLEAR_0:
+ case WCD938X_DIGITAL_INTR_CLEAR_1:
+ case WCD938X_DIGITAL_INTR_CLEAR_2:
+ case WCD938X_DIGITAL_INTR_LEVEL_0:
+ case WCD938X_DIGITAL_INTR_LEVEL_1:
+ case WCD938X_DIGITAL_INTR_LEVEL_2:
+ case WCD938X_DIGITAL_INTR_SET_0:
+ case WCD938X_DIGITAL_INTR_SET_1:
+ case WCD938X_DIGITAL_INTR_SET_2:
+ case WCD938X_DIGITAL_INTR_TEST_0:
+ case WCD938X_DIGITAL_INTR_TEST_1:
+ case WCD938X_DIGITAL_INTR_TEST_2:
+ case WCD938X_DIGITAL_TX_MODE_DBG_EN:
+ case WCD938X_DIGITAL_TX_MODE_DBG_0_1:
+ case WCD938X_DIGITAL_TX_MODE_DBG_2_3:
+ case WCD938X_DIGITAL_LB_IN_SEL_CTL:
+ case WCD938X_DIGITAL_LOOP_BACK_MODE:
+ case WCD938X_DIGITAL_SWR_DAC_TEST:
+ case WCD938X_DIGITAL_SWR_HM_TEST_RX_0:
+ case WCD938X_DIGITAL_SWR_HM_TEST_TX_0:
+ case WCD938X_DIGITAL_SWR_HM_TEST_RX_1:
+ case WCD938X_DIGITAL_SWR_HM_TEST_TX_1:
+ case WCD938X_DIGITAL_SWR_HM_TEST_TX_2:
+ case WCD938X_DIGITAL_PAD_CTL_SWR_0:
+ case WCD938X_DIGITAL_PAD_CTL_SWR_1:
+ case WCD938X_DIGITAL_I2C_CTL:
+ case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE:
+ case WCD938X_DIGITAL_EFUSE_TEST_CTL_0:
+ case WCD938X_DIGITAL_EFUSE_TEST_CTL_1:
+ case WCD938X_DIGITAL_PAD_CTL_PDM_RX0:
+ case WCD938X_DIGITAL_PAD_CTL_PDM_RX1:
+ case WCD938X_DIGITAL_PAD_CTL_PDM_TX0:
+ case WCD938X_DIGITAL_PAD_CTL_PDM_TX1:
+ case WCD938X_DIGITAL_PAD_CTL_PDM_TX2:
+ case WCD938X_DIGITAL_PAD_INP_DIS_0:
+ case WCD938X_DIGITAL_PAD_INP_DIS_1:
+ case WCD938X_DIGITAL_DRIVE_STRENGTH_0:
+ case WCD938X_DIGITAL_DRIVE_STRENGTH_1:
+ case WCD938X_DIGITAL_DRIVE_STRENGTH_2:
+ case WCD938X_DIGITAL_RX_DATA_EDGE_CTL:
+ case WCD938X_DIGITAL_TX_DATA_EDGE_CTL:
+ case WCD938X_DIGITAL_GPIO_MODE:
+ case WCD938X_DIGITAL_PIN_CTL_OE:
+ case WCD938X_DIGITAL_PIN_CTL_DATA_0:
+ case WCD938X_DIGITAL_PIN_CTL_DATA_1:
+ case WCD938X_DIGITAL_DIG_DEBUG_CTL:
+ case WCD938X_DIGITAL_DIG_DEBUG_EN:
+ case WCD938X_DIGITAL_ANA_CSR_DBG_ADD:
+ case WCD938X_DIGITAL_ANA_CSR_DBG_CTL:
+ case WCD938X_DIGITAL_SSP_DBG:
+ case WCD938X_DIGITAL_SPARE_0:
+ case WCD938X_DIGITAL_SPARE_1:
+ case WCD938X_DIGITAL_SPARE_2:
+ case WCD938X_DIGITAL_TX_REQ_FB_CTL_0:
+ case WCD938X_DIGITAL_TX_REQ_FB_CTL_1:
+ case WCD938X_DIGITAL_TX_REQ_FB_CTL_2:
+ case WCD938X_DIGITAL_TX_REQ_FB_CTL_3:
+ case WCD938X_DIGITAL_TX_REQ_FB_CTL_4:
+ case WCD938X_DIGITAL_DEM_BYPASS_DATA0:
+ case WCD938X_DIGITAL_DEM_BYPASS_DATA1:
+ case WCD938X_DIGITAL_DEM_BYPASS_DATA2:
+ case WCD938X_DIGITAL_DEM_BYPASS_DATA3:
+ return true;
+ }
+
+ return false;
+}
+
+static bool wcd938x_readonly_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case WCD938X_ANA_MBHC_RESULT_1:
+ case WCD938X_ANA_MBHC_RESULT_2:
+ case WCD938X_ANA_MBHC_RESULT_3:
+ case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS:
+ case WCD938X_TX_1_2_SAR2_ERR:
+ case WCD938X_TX_1_2_SAR1_ERR:
+ case WCD938X_TX_3_4_SAR4_ERR:
+ case WCD938X_TX_3_4_SAR3_ERR:
+ case WCD938X_HPH_L_STATUS:
+ case WCD938X_HPH_R_STATUS:
+ case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS:
+ case WCD938X_EAR_STATUS_REG_1:
+ case WCD938X_EAR_STATUS_REG_2:
+ case WCD938X_MBHC_NEW_FSM_STATUS:
+ case WCD938X_MBHC_NEW_ADC_RESULT:
+ case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT:
+ case WCD938X_AUX_INT_STATUS_REG:
+ case WCD938X_LDORXTX_INT_STATUS:
+ case WCD938X_DIGITAL_CHIP_ID0:
+ case WCD938X_DIGITAL_CHIP_ID1:
+ case WCD938X_DIGITAL_CHIP_ID2:
+ case WCD938X_DIGITAL_CHIP_ID3:
+ case WCD938X_DIGITAL_INTR_STATUS_0:
+ case WCD938X_DIGITAL_INTR_STATUS_1:
+ case WCD938X_DIGITAL_INTR_STATUS_2:
+ case WCD938X_DIGITAL_INTR_CLEAR_0:
+ case WCD938X_DIGITAL_INTR_CLEAR_1:
+ case WCD938X_DIGITAL_INTR_CLEAR_2:
+ case WCD938X_DIGITAL_SWR_HM_TEST_0:
+ case WCD938X_DIGITAL_SWR_HM_TEST_1:
+ case WCD938X_DIGITAL_EFUSE_T_DATA_0:
+ case WCD938X_DIGITAL_EFUSE_T_DATA_1:
+ case WCD938X_DIGITAL_PIN_STATUS_0:
+ case WCD938X_DIGITAL_PIN_STATUS_1:
+ case WCD938X_DIGITAL_MODE_STATUS_0:
+ case WCD938X_DIGITAL_MODE_STATUS_1:
+ case WCD938X_DIGITAL_EFUSE_REG_0:
+ case WCD938X_DIGITAL_EFUSE_REG_1:
+ case WCD938X_DIGITAL_EFUSE_REG_2:
+ case WCD938X_DIGITAL_EFUSE_REG_3:
+ case WCD938X_DIGITAL_EFUSE_REG_4:
+ case WCD938X_DIGITAL_EFUSE_REG_5:
+ case WCD938X_DIGITAL_EFUSE_REG_6:
+ case WCD938X_DIGITAL_EFUSE_REG_7:
+ case WCD938X_DIGITAL_EFUSE_REG_8:
+ case WCD938X_DIGITAL_EFUSE_REG_9:
+ case WCD938X_DIGITAL_EFUSE_REG_10:
+ case WCD938X_DIGITAL_EFUSE_REG_11:
+ case WCD938X_DIGITAL_EFUSE_REG_12:
+ case WCD938X_DIGITAL_EFUSE_REG_13:
+ case WCD938X_DIGITAL_EFUSE_REG_14:
+ case WCD938X_DIGITAL_EFUSE_REG_15:
+ case WCD938X_DIGITAL_EFUSE_REG_16:
+ case WCD938X_DIGITAL_EFUSE_REG_17:
+ case WCD938X_DIGITAL_EFUSE_REG_18:
+ case WCD938X_DIGITAL_EFUSE_REG_19:
+ case WCD938X_DIGITAL_EFUSE_REG_20:
+ case WCD938X_DIGITAL_EFUSE_REG_21:
+ case WCD938X_DIGITAL_EFUSE_REG_22:
+ case WCD938X_DIGITAL_EFUSE_REG_23:
+ case WCD938X_DIGITAL_EFUSE_REG_24:
+ case WCD938X_DIGITAL_EFUSE_REG_25:
+ case WCD938X_DIGITAL_EFUSE_REG_26:
+ case WCD938X_DIGITAL_EFUSE_REG_27:
+ case WCD938X_DIGITAL_EFUSE_REG_28:
+ case WCD938X_DIGITAL_EFUSE_REG_29:
+ case WCD938X_DIGITAL_EFUSE_REG_30:
+ case WCD938X_DIGITAL_EFUSE_REG_31:
+ return true;
+ }
+ return false;
+}
+
+static bool wcd938x_readable_register(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+ ret = wcd938x_readonly_register(dev, reg);
+ if (!ret)
+ return wcd938x_rdwr_register(dev, reg);
+
+ return ret;
+}
+
+static bool wcd938x_writeable_register(struct device *dev, unsigned int reg)
+{
+ return wcd938x_rdwr_register(dev, reg);
+}
+
+static bool wcd938x_volatile_register(struct device *dev, unsigned int reg)
+{
+ if (reg <= WCD938X_BASE_ADDRESS)
+ return false;
+
+ if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE)
+ return true;
+
+ if (wcd938x_readonly_register(dev, reg))
+ return true;
+
+ return false;
+}
+
+static const struct regmap_config wcd938x_regmap_config = {
+ .name = "wcd938x_csr",
+ .reg_bits = 32,
+ .val_bits = 8,
+ .cache_type = REGCACHE_RBTREE,
+ .reg_defaults = wcd938x_defaults,
+ .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults),
+ .max_register = WCD938X_MAX_REGISTER,
+ .readable_reg = wcd938x_readable_register,
+ .writeable_reg = wcd938x_writeable_register,
+ .volatile_reg = wcd938x_volatile_register,
+ .can_multi_write = true,
+};
+
+static const struct sdw_slave_ops wcd9380_slave_ops = {
.update_status = wcd9380_update_status,
.interrupt_callback = wcd9380_interrupt_callback,
.bus_config = wcd9380_bus_config,
@@ -261,6 +1263,16 @@ static int wcd9380_probe(struct sdw_slave *pdev,
wcd->ch_info = &wcd938x_sdw_rx_ch_info[0];
}
+ if (wcd->is_tx) {
+ wcd->regmap = devm_regmap_init_sdw(pdev, &wcd938x_regmap_config);
+ if (IS_ERR(wcd->regmap))
+ return dev_err_probe(dev, PTR_ERR(wcd->regmap),
+ "Regmap init failed\n");
+
+ /* Start in cache-only until device is enumerated */
+ regcache_cache_only(wcd->regmap, true);
+ };
+
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
@@ -278,22 +1290,23 @@ MODULE_DEVICE_TABLE(sdw, wcd9380_slave_id);
static int __maybe_unused wcd938x_sdw_runtime_suspend(struct device *dev)
{
- struct regmap *regmap = dev_get_regmap(dev, NULL);
+ struct wcd938x_sdw_priv *wcd = dev_get_drvdata(dev);
- if (regmap) {
- regcache_cache_only(regmap, true);
- regcache_mark_dirty(regmap);
+ if (wcd->regmap) {
+ regcache_cache_only(wcd->regmap, true);
+ regcache_mark_dirty(wcd->regmap);
}
+
return 0;
}
static int __maybe_unused wcd938x_sdw_runtime_resume(struct device *dev)
{
- struct regmap *regmap = dev_get_regmap(dev, NULL);
+ struct wcd938x_sdw_priv *wcd = dev_get_drvdata(dev);
- if (regmap) {
- regcache_cache_only(regmap, false);
- regcache_sync(regmap);
+ if (wcd->regmap) {
+ regcache_cache_only(wcd->regmap, false);
+ regcache_sync(wcd->regmap);
}
pm_runtime_mark_last_busy(dev);
diff --git a/sound/soc/codecs/wcd938x.c b/sound/soc/codecs/wcd938x.c
index aca06a4026f3..1d801a7b1469 100644
--- a/sound/soc/codecs/wcd938x.c
+++ b/sound/soc/codecs/wcd938x.c
@@ -273,1001 +273,6 @@ static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02),
};
-static const struct reg_default wcd938x_defaults[] = {
- {WCD938X_ANA_PAGE_REGISTER, 0x00},
- {WCD938X_ANA_BIAS, 0x00},
- {WCD938X_ANA_RX_SUPPLIES, 0x00},
- {WCD938X_ANA_HPH, 0x0C},
- {WCD938X_ANA_EAR, 0x00},
- {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02},
- {WCD938X_ANA_TX_CH1, 0x20},
- {WCD938X_ANA_TX_CH2, 0x00},
- {WCD938X_ANA_TX_CH3, 0x20},
- {WCD938X_ANA_TX_CH4, 0x00},
- {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00},
- {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00},
- {WCD938X_ANA_MBHC_MECH, 0x39},
- {WCD938X_ANA_MBHC_ELECT, 0x08},
- {WCD938X_ANA_MBHC_ZDET, 0x00},
- {WCD938X_ANA_MBHC_RESULT_1, 0x00},
- {WCD938X_ANA_MBHC_RESULT_2, 0x00},
- {WCD938X_ANA_MBHC_RESULT_3, 0x00},
- {WCD938X_ANA_MBHC_BTN0, 0x00},
- {WCD938X_ANA_MBHC_BTN1, 0x10},
- {WCD938X_ANA_MBHC_BTN2, 0x20},
- {WCD938X_ANA_MBHC_BTN3, 0x30},
- {WCD938X_ANA_MBHC_BTN4, 0x40},
- {WCD938X_ANA_MBHC_BTN5, 0x50},
- {WCD938X_ANA_MBHC_BTN6, 0x60},
- {WCD938X_ANA_MBHC_BTN7, 0x70},
- {WCD938X_ANA_MICB1, 0x10},
- {WCD938X_ANA_MICB2, 0x10},
- {WCD938X_ANA_MICB2_RAMP, 0x00},
- {WCD938X_ANA_MICB3, 0x10},
- {WCD938X_ANA_MICB4, 0x10},
- {WCD938X_BIAS_CTL, 0x2A},
- {WCD938X_BIAS_VBG_FINE_ADJ, 0x55},
- {WCD938X_LDOL_VDDCX_ADJUST, 0x01},
- {WCD938X_LDOL_DISABLE_LDOL, 0x00},
- {WCD938X_MBHC_CTL_CLK, 0x00},
- {WCD938X_MBHC_CTL_ANA, 0x00},
- {WCD938X_MBHC_CTL_SPARE_1, 0x00},
- {WCD938X_MBHC_CTL_SPARE_2, 0x00},
- {WCD938X_MBHC_CTL_BCS, 0x00},
- {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00},
- {WCD938X_MBHC_TEST_CTL, 0x00},
- {WCD938X_LDOH_MODE, 0x2B},
- {WCD938X_LDOH_BIAS, 0x68},
- {WCD938X_LDOH_STB_LOADS, 0x00},
- {WCD938X_LDOH_SLOWRAMP, 0x50},
- {WCD938X_MICB1_TEST_CTL_1, 0x1A},
- {WCD938X_MICB1_TEST_CTL_2, 0x00},
- {WCD938X_MICB1_TEST_CTL_3, 0xA4},
- {WCD938X_MICB2_TEST_CTL_1, 0x1A},
- {WCD938X_MICB2_TEST_CTL_2, 0x00},
- {WCD938X_MICB2_TEST_CTL_3, 0x24},
- {WCD938X_MICB3_TEST_CTL_1, 0x1A},
- {WCD938X_MICB3_TEST_CTL_2, 0x00},
- {WCD938X_MICB3_TEST_CTL_3, 0xA4},
- {WCD938X_MICB4_TEST_CTL_1, 0x1A},
- {WCD938X_MICB4_TEST_CTL_2, 0x00},
- {WCD938X_MICB4_TEST_CTL_3, 0xA4},
- {WCD938X_TX_COM_ADC_VCM, 0x39},
- {WCD938X_TX_COM_BIAS_ATEST, 0xE0},
- {WCD938X_TX_COM_SPARE1, 0x00},
- {WCD938X_TX_COM_SPARE2, 0x00},
- {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22},
- {WCD938X_TX_COM_TXFE_DIV_START, 0x00},
- {WCD938X_TX_COM_SPARE3, 0x00},
- {WCD938X_TX_COM_SPARE4, 0x00},
- {WCD938X_TX_1_2_TEST_EN, 0xCC},
- {WCD938X_TX_1_2_ADC_IB, 0xE9},
- {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A},
- {WCD938X_TX_1_2_TEST_CTL, 0x38},
- {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF},
- {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00},
- {WCD938X_TX_1_2_SAR2_ERR, 0x00},
- {WCD938X_TX_1_2_SAR1_ERR, 0x00},
- {WCD938X_TX_3_4_TEST_EN, 0xCC},
- {WCD938X_TX_3_4_ADC_IB, 0xE9},
- {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A},
- {WCD938X_TX_3_4_TEST_CTL, 0x38},
- {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF},
- {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00},
- {WCD938X_TX_3_4_SAR4_ERR, 0x00},
- {WCD938X_TX_3_4_SAR3_ERR, 0x00},
- {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB},
- {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00},
- {WCD938X_TX_3_4_SPARE1, 0x00},
- {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB},
- {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00},
- {WCD938X_TX_3_4_SPARE2, 0x00},
- {WCD938X_CLASSH_MODE_1, 0x40},
- {WCD938X_CLASSH_MODE_2, 0x3A},
- {WCD938X_CLASSH_MODE_3, 0x00},
- {WCD938X_CLASSH_CTRL_VCL_1, 0x70},
- {WCD938X_CLASSH_CTRL_VCL_2, 0x82},
- {WCD938X_CLASSH_CTRL_CCL_1, 0x31},
- {WCD938X_CLASSH_CTRL_CCL_2, 0x80},
- {WCD938X_CLASSH_CTRL_CCL_3, 0x80},
- {WCD938X_CLASSH_CTRL_CCL_4, 0x51},
- {WCD938X_CLASSH_CTRL_CCL_5, 0x00},
- {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00},
- {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77},
- {WCD938X_CLASSH_SPARE, 0x00},
- {WCD938X_FLYBACK_EN, 0x4E},
- {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B},
- {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45},
- {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74},
- {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F},
- {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83},
- {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98},
- {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9},
- {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68},
- {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64},
- {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED},
- {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0},
- {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6},
- {WCD938X_FLYBACK_CTRL_1, 0x65},
- {WCD938X_FLYBACK_TEST_CTL, 0x00},
- {WCD938X_RX_AUX_SW_CTL, 0x00},
- {WCD938X_RX_PA_AUX_IN_CONN, 0x01},
- {WCD938X_RX_TIMER_DIV, 0x32},
- {WCD938X_RX_OCP_CTL, 0x1F},
- {WCD938X_RX_OCP_COUNT, 0x77},
- {WCD938X_RX_BIAS_EAR_DAC, 0xA0},
- {WCD938X_RX_BIAS_EAR_AMP, 0xAA},
- {WCD938X_RX_BIAS_HPH_LDO, 0xA9},
- {WCD938X_RX_BIAS_HPH_PA, 0xAA},
- {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A},
- {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88},
- {WCD938X_RX_BIAS_HPH_CNP1, 0x82},
- {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82},
- {WCD938X_RX_BIAS_AUX_DAC, 0xA0},
- {WCD938X_RX_BIAS_AUX_AMP, 0xAA},
- {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50},
- {WCD938X_RX_BIAS_MISC, 0x00},
- {WCD938X_RX_BIAS_BUCK_RST, 0x08},
- {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44},
- {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40},
- {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA},
- {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14},
- {WCD938X_HPH_L_STATUS, 0x04},
- {WCD938X_HPH_R_STATUS, 0x04},
- {WCD938X_HPH_CNP_EN, 0x80},
- {WCD938X_HPH_CNP_WG_CTL, 0x9A},
- {WCD938X_HPH_CNP_WG_TIME, 0x14},
- {WCD938X_HPH_OCP_CTL, 0x28},
- {WCD938X_HPH_AUTO_CHOP, 0x16},
- {WCD938X_HPH_CHOP_CTL, 0x83},
- {WCD938X_HPH_PA_CTL1, 0x46},
- {WCD938X_HPH_PA_CTL2, 0x50},
- {WCD938X_HPH_L_EN, 0x80},
- {WCD938X_HPH_L_TEST, 0xE0},
- {WCD938X_HPH_L_ATEST, 0x50},
- {WCD938X_HPH_R_EN, 0x80},
- {WCD938X_HPH_R_TEST, 0xE0},
- {WCD938X_HPH_R_ATEST, 0x54},
- {WCD938X_HPH_RDAC_CLK_CTL1, 0x99},
- {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B},
- {WCD938X_HPH_RDAC_LDO_CTL, 0x33},
- {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00},
- {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68},
- {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E},
- {WCD938X_HPH_L_DAC_CTL, 0x20},
- {WCD938X_HPH_R_DAC_CTL, 0x20},
- {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55},
- {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19},
- {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0},
- {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00},
- {WCD938X_EAR_EAR_EN_REG, 0x22},
- {WCD938X_EAR_EAR_PA_CON, 0x44},
- {WCD938X_EAR_EAR_SP_CON, 0xDB},
- {WCD938X_EAR_EAR_DAC_CON, 0x80},
- {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2},
- {WCD938X_EAR_TEST_CTL, 0x00},
- {WCD938X_EAR_STATUS_REG_1, 0x00},
- {WCD938X_EAR_STATUS_REG_2, 0x08},
- {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00},
- {WCD938X_HPH_NEW_ANA_HPH2, 0x00},
- {WCD938X_HPH_NEW_ANA_HPH3, 0x00},
- {WCD938X_SLEEP_CTL, 0x16},
- {WCD938X_SLEEP_WATCHDOG_CTL, 0x00},
- {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00},
- {WCD938X_MBHC_NEW_CTL_1, 0x02},
- {WCD938X_MBHC_NEW_CTL_2, 0x05},
- {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9},
- {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F},
- {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00},
- {WCD938X_MBHC_NEW_FSM_STATUS, 0x00},
- {WCD938X_MBHC_NEW_ADC_RESULT, 0x00},
- {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00},
- {WCD938X_AUX_AUXPA, 0x00},
- {WCD938X_LDORXTX_MODE, 0x0C},
- {WCD938X_LDORXTX_CONFIG, 0x10},
- {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00},
- {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00},
- {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40},
- {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81},
- {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10},
- {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00},
- {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81},
- {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22},
- {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00},
- {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00},
- {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE},
- {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02},
- {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E},
- {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54},
- {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00},
- {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00},
- {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90},
- {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90},
- {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62},
- {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01},
- {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11},
- {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57},
- {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01},
- {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00},
- {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00},
- {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8},
- {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42},
- {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22},
- {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00},
- {WCD938X_AUX_INT_EN_REG, 0x00},
- {WCD938X_AUX_INT_PA_CTRL, 0x06},
- {WCD938X_AUX_INT_SP_CTRL, 0xD2},
- {WCD938X_AUX_INT_DAC_CTRL, 0x80},
- {WCD938X_AUX_INT_CLK_CTRL, 0x50},
- {WCD938X_AUX_INT_TEST_CTRL, 0x00},
- {WCD938X_AUX_INT_STATUS_REG, 0x00},
- {WCD938X_AUX_INT_MISC, 0x00},
- {WCD938X_LDORXTX_INT_BIAS, 0x6E},
- {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50},
- {WCD938X_LDORXTX_INT_TEST0, 0x1C},
- {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF},
- {WCD938X_LDORXTX_INT_TEST1, 0x1F},
- {WCD938X_LDORXTX_INT_STATUS, 0x00},
- {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A},
- {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A},
- {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02},
- {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60},
- {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF},
- {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F},
- {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F},
- {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F},
- {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F},
- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7},
- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8},
- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6},
- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5},
- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA},
- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05},
- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5},
- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13},
- {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88},
- {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42},
- {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF},
- {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64},
- {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64},
- {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77},
- {WCD938X_DIGITAL_PAGE_REGISTER, 0x00},
- {WCD938X_DIGITAL_CHIP_ID0, 0x00},
- {WCD938X_DIGITAL_CHIP_ID1, 0x00},
- {WCD938X_DIGITAL_CHIP_ID2, 0x0D},
- {WCD938X_DIGITAL_CHIP_ID3, 0x01},
- {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00},
- {WCD938X_DIGITAL_CDC_RST_CTL, 0x03},
- {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00},
- {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00},
- {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0},
- {WCD938X_DIGITAL_SWR_RST_EN, 0x00},
- {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55},
- {WCD938X_DIGITAL_CDC_RX_RST, 0x00},
- {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC},
- {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC},
- {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC},
- {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00},
- {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00},
- {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00},
- {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7},
- {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8},
- {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47},
- {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43},
- {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1},
- {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17},
- {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D},
- {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29},
- {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34},
- {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59},
- {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66},
- {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87},
- {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA},
- {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3},
- {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69},
- {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54},
- {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02},
- {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15},
- {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4},
- {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5},
- {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86},
- {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85},
- {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA},
- {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2},
- {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62},
- {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55},
- {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9},
- {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D},
- {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E},
- {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01},
- {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00},
- {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC},
- {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01},
- {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00},
- {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00},
- {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00},
- {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00},
- {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00},
- {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68},
- {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68},
- {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68},
- {WCD938X_DIGITAL_CDC_TX_RST, 0x00},
- {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01},
- {WCD938X_DIGITAL_CDC_RST, 0x00},
- {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F},
- {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04},
- {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01},
- {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01},
- {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01},
- {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01},
- {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00},
- {WCD938X_DIGITAL_EFUSE_CTL, 0x2B},
- {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11},
- {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11},
- {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00},
- {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00},
- {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00},
- {WCD938X_DIGITAL_INTR_MODE, 0x00},
- {WCD938X_DIGITAL_INTR_MASK_0, 0xFF},
- {WCD938X_DIGITAL_INTR_MASK_1, 0xFF},
- {WCD938X_DIGITAL_INTR_MASK_2, 0x3F},
- {WCD938X_DIGITAL_INTR_STATUS_0, 0x00},
- {WCD938X_DIGITAL_INTR_STATUS_1, 0x00},
- {WCD938X_DIGITAL_INTR_STATUS_2, 0x00},
- {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00},
- {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00},
- {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00},
- {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00},
- {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00},
- {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00},
- {WCD938X_DIGITAL_INTR_SET_0, 0x00},
- {WCD938X_DIGITAL_INTR_SET_1, 0x00},
- {WCD938X_DIGITAL_INTR_SET_2, 0x00},
- {WCD938X_DIGITAL_INTR_TEST_0, 0x00},
- {WCD938X_DIGITAL_INTR_TEST_1, 0x00},
- {WCD938X_DIGITAL_INTR_TEST_2, 0x00},
- {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00},
- {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00},
- {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00},
- {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00},
- {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00},
- {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00},
- {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40},
- {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40},
- {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00},
- {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00},
- {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00},
- {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00},
- {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00},
- {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F},
- {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06},
- {WCD938X_DIGITAL_I2C_CTL, 0x00},
- {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00},
- {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00},
- {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00},
- {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00},
- {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00},
- {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1},
- {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1},
- {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1},
- {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1},
- {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1},
- {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00},
- {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00},
- {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00},
- {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00},
- {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00},
- {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F},
- {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80},
- {WCD938X_DIGITAL_GPIO_MODE, 0x00},
- {WCD938X_DIGITAL_PIN_CTL_OE, 0x00},
- {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00},
- {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00},
- {WCD938X_DIGITAL_PIN_STATUS_0, 0x00},
- {WCD938X_DIGITAL_PIN_STATUS_1, 0x00},
- {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00},
- {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00},
- {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00},
- {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48},
- {WCD938X_DIGITAL_SSP_DBG, 0x00},
- {WCD938X_DIGITAL_MODE_STATUS_0, 0x00},
- {WCD938X_DIGITAL_MODE_STATUS_1, 0x00},
- {WCD938X_DIGITAL_SPARE_0, 0x00},
- {WCD938X_DIGITAL_SPARE_1, 0x00},
- {WCD938X_DIGITAL_SPARE_2, 0x00},
- {WCD938X_DIGITAL_EFUSE_REG_0, 0x00},
- {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF},
- {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E},
- {WCD938X_DIGITAL_EFUSE_REG_21, 0x00},
- {WCD938X_DIGITAL_EFUSE_REG_22, 0x00},
- {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8},
- {WCD938X_DIGITAL_EFUSE_REG_24, 0x16},
- {WCD938X_DIGITAL_EFUSE_REG_25, 0x00},
- {WCD938X_DIGITAL_EFUSE_REG_26, 0x00},
- {WCD938X_DIGITAL_EFUSE_REG_27, 0x00},
- {WCD938X_DIGITAL_EFUSE_REG_28, 0x00},
- {WCD938X_DIGITAL_EFUSE_REG_29, 0x00},
- {WCD938X_DIGITAL_EFUSE_REG_30, 0x00},
- {WCD938X_DIGITAL_EFUSE_REG_31, 0x00},
- {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88},
- {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88},
- {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88},
- {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88},
- {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88},
- {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55},
- {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55},
- {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55},
- {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01},
-};
-
-static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg)
-{
- switch (reg) {
- case WCD938X_ANA_PAGE_REGISTER:
- case WCD938X_ANA_BIAS:
- case WCD938X_ANA_RX_SUPPLIES:
- case WCD938X_ANA_HPH:
- case WCD938X_ANA_EAR:
- case WCD938X_ANA_EAR_COMPANDER_CTL:
- case WCD938X_ANA_TX_CH1:
- case WCD938X_ANA_TX_CH2:
- case WCD938X_ANA_TX_CH3:
- case WCD938X_ANA_TX_CH4:
- case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC:
- case WCD938X_ANA_MICB3_DSP_EN_LOGIC:
- case WCD938X_ANA_MBHC_MECH:
- case WCD938X_ANA_MBHC_ELECT:
- case WCD938X_ANA_MBHC_ZDET:
- case WCD938X_ANA_MBHC_BTN0:
- case WCD938X_ANA_MBHC_BTN1:
- case WCD938X_ANA_MBHC_BTN2:
- case WCD938X_ANA_MBHC_BTN3:
- case WCD938X_ANA_MBHC_BTN4:
- case WCD938X_ANA_MBHC_BTN5:
- case WCD938X_ANA_MBHC_BTN6:
- case WCD938X_ANA_MBHC_BTN7:
- case WCD938X_ANA_MICB1:
- case WCD938X_ANA_MICB2:
- case WCD938X_ANA_MICB2_RAMP:
- case WCD938X_ANA_MICB3:
- case WCD938X_ANA_MICB4:
- case WCD938X_BIAS_CTL:
- case WCD938X_BIAS_VBG_FINE_ADJ:
- case WCD938X_LDOL_VDDCX_ADJUST:
- case WCD938X_LDOL_DISABLE_LDOL:
- case WCD938X_MBHC_CTL_CLK:
- case WCD938X_MBHC_CTL_ANA:
- case WCD938X_MBHC_CTL_SPARE_1:
- case WCD938X_MBHC_CTL_SPARE_2:
- case WCD938X_MBHC_CTL_BCS:
- case WCD938X_MBHC_TEST_CTL:
- case WCD938X_LDOH_MODE:
- case WCD938X_LDOH_BIAS:
- case WCD938X_LDOH_STB_LOADS:
- case WCD938X_LDOH_SLOWRAMP:
- case WCD938X_MICB1_TEST_CTL_1:
- case WCD938X_MICB1_TEST_CTL_2:
- case WCD938X_MICB1_TEST_CTL_3:
- case WCD938X_MICB2_TEST_CTL_1:
- case WCD938X_MICB2_TEST_CTL_2:
- case WCD938X_MICB2_TEST_CTL_3:
- case WCD938X_MICB3_TEST_CTL_1:
- case WCD938X_MICB3_TEST_CTL_2:
- case WCD938X_MICB3_TEST_CTL_3:
- case WCD938X_MICB4_TEST_CTL_1:
- case WCD938X_MICB4_TEST_CTL_2:
- case WCD938X_MICB4_TEST_CTL_3:
- case WCD938X_TX_COM_ADC_VCM:
- case WCD938X_TX_COM_BIAS_ATEST:
- case WCD938X_TX_COM_SPARE1:
- case WCD938X_TX_COM_SPARE2:
- case WCD938X_TX_COM_TXFE_DIV_CTL:
- case WCD938X_TX_COM_TXFE_DIV_START:
- case WCD938X_TX_COM_SPARE3:
- case WCD938X_TX_COM_SPARE4:
- case WCD938X_TX_1_2_TEST_EN:
- case WCD938X_TX_1_2_ADC_IB:
- case WCD938X_TX_1_2_ATEST_REFCTL:
- case WCD938X_TX_1_2_TEST_CTL:
- case WCD938X_TX_1_2_TEST_BLK_EN1:
- case WCD938X_TX_1_2_TXFE1_CLKDIV:
- case WCD938X_TX_3_4_TEST_EN:
- case WCD938X_TX_3_4_ADC_IB:
- case WCD938X_TX_3_4_ATEST_REFCTL:
- case WCD938X_TX_3_4_TEST_CTL:
- case WCD938X_TX_3_4_TEST_BLK_EN3:
- case WCD938X_TX_3_4_TXFE3_CLKDIV:
- case WCD938X_TX_3_4_TEST_BLK_EN2:
- case WCD938X_TX_3_4_TXFE2_CLKDIV:
- case WCD938X_TX_3_4_SPARE1:
- case WCD938X_TX_3_4_TEST_BLK_EN4:
- case WCD938X_TX_3_4_TXFE4_CLKDIV:
- case WCD938X_TX_3_4_SPARE2:
- case WCD938X_CLASSH_MODE_1:
- case WCD938X_CLASSH_MODE_2:
- case WCD938X_CLASSH_MODE_3:
- case WCD938X_CLASSH_CTRL_VCL_1:
- case WCD938X_CLASSH_CTRL_VCL_2:
- case WCD938X_CLASSH_CTRL_CCL_1:
- case WCD938X_CLASSH_CTRL_CCL_2:
- case WCD938X_CLASSH_CTRL_CCL_3:
- case WCD938X_CLASSH_CTRL_CCL_4:
- case WCD938X_CLASSH_CTRL_CCL_5:
- case WCD938X_CLASSH_BUCK_TMUX_A_D:
- case WCD938X_CLASSH_BUCK_SW_DRV_CNTL:
- case WCD938X_CLASSH_SPARE:
- case WCD938X_FLYBACK_EN:
- case WCD938X_FLYBACK_VNEG_CTRL_1:
- case WCD938X_FLYBACK_VNEG_CTRL_2:
- case WCD938X_FLYBACK_VNEG_CTRL_3:
- case WCD938X_FLYBACK_VNEG_CTRL_4:
- case WCD938X_FLYBACK_VNEG_CTRL_5:
- case WCD938X_FLYBACK_VNEG_CTRL_6:
- case WCD938X_FLYBACK_VNEG_CTRL_7:
- case WCD938X_FLYBACK_VNEG_CTRL_8:
- case WCD938X_FLYBACK_VNEG_CTRL_9:
- case WCD938X_FLYBACK_VNEGDAC_CTRL_1:
- case WCD938X_FLYBACK_VNEGDAC_CTRL_2:
- case WCD938X_FLYBACK_VNEGDAC_CTRL_3:
- case WCD938X_FLYBACK_CTRL_1:
- case WCD938X_FLYBACK_TEST_CTL:
- case WCD938X_RX_AUX_SW_CTL:
- case WCD938X_RX_PA_AUX_IN_CONN:
- case WCD938X_RX_TIMER_DIV:
- case WCD938X_RX_OCP_CTL:
- case WCD938X_RX_OCP_COUNT:
- case WCD938X_RX_BIAS_EAR_DAC:
- case WCD938X_RX_BIAS_EAR_AMP:
- case WCD938X_RX_BIAS_HPH_LDO:
- case WCD938X_RX_BIAS_HPH_PA:
- case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2:
- case WCD938X_RX_BIAS_HPH_RDAC_LDO:
- case WCD938X_RX_BIAS_HPH_CNP1:
- case WCD938X_RX_BIAS_HPH_LOWPOWER:
- case WCD938X_RX_BIAS_AUX_DAC:
- case WCD938X_RX_BIAS_AUX_AMP:
- case WCD938X_RX_BIAS_VNEGDAC_BLEEDER:
- case WCD938X_RX_BIAS_MISC:
- case WCD938X_RX_BIAS_BUCK_RST:
- case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP:
- case WCD938X_RX_BIAS_FLYB_ERRAMP:
- case WCD938X_RX_BIAS_FLYB_BUFF:
- case WCD938X_RX_BIAS_FLYB_MID_RST:
- case WCD938X_HPH_CNP_EN:
- case WCD938X_HPH_CNP_WG_CTL:
- case WCD938X_HPH_CNP_WG_TIME:
- case WCD938X_HPH_OCP_CTL:
- case WCD938X_HPH_AUTO_CHOP:
- case WCD938X_HPH_CHOP_CTL:
- case WCD938X_HPH_PA_CTL1:
- case WCD938X_HPH_PA_CTL2:
- case WCD938X_HPH_L_EN:
- case WCD938X_HPH_L_TEST:
- case WCD938X_HPH_L_ATEST:
- case WCD938X_HPH_R_EN:
- case WCD938X_HPH_R_TEST:
- case WCD938X_HPH_R_ATEST:
- case WCD938X_HPH_RDAC_CLK_CTL1:
- case WCD938X_HPH_RDAC_CLK_CTL2:
- case WCD938X_HPH_RDAC_LDO_CTL:
- case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL:
- case WCD938X_HPH_REFBUFF_UHQA_CTL:
- case WCD938X_HPH_REFBUFF_LP_CTL:
- case WCD938X_HPH_L_DAC_CTL:
- case WCD938X_HPH_R_DAC_CTL:
- case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL:
- case WCD938X_HPH_SURGE_HPHLR_SURGE_EN:
- case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1:
- case WCD938X_EAR_EAR_EN_REG:
- case WCD938X_EAR_EAR_PA_CON:
- case WCD938X_EAR_EAR_SP_CON:
- case WCD938X_EAR_EAR_DAC_CON:
- case WCD938X_EAR_EAR_CNP_FSM_CON:
- case WCD938X_EAR_TEST_CTL:
- case WCD938X_ANA_NEW_PAGE_REGISTER:
- case WCD938X_HPH_NEW_ANA_HPH2:
- case WCD938X_HPH_NEW_ANA_HPH3:
- case WCD938X_SLEEP_CTL:
- case WCD938X_SLEEP_WATCHDOG_CTL:
- case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL:
- case WCD938X_MBHC_NEW_CTL_1:
- case WCD938X_MBHC_NEW_CTL_2:
- case WCD938X_MBHC_NEW_PLUG_DETECT_CTL:
- case WCD938X_MBHC_NEW_ZDET_ANA_CTL:
- case WCD938X_MBHC_NEW_ZDET_RAMP_CTL:
- case WCD938X_TX_NEW_AMIC_MUX_CFG:
- case WCD938X_AUX_AUXPA:
- case WCD938X_LDORXTX_MODE:
- case WCD938X_LDORXTX_CONFIG:
- case WCD938X_DIE_CRACK_DIE_CRK_DET_EN:
- case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL:
- case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L:
- case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL:
- case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL:
- case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R:
- case WCD938X_HPH_NEW_INT_PA_MISC1:
- case WCD938X_HPH_NEW_INT_PA_MISC2:
- case WCD938X_HPH_NEW_INT_PA_RDAC_MISC:
- case WCD938X_HPH_NEW_INT_HPH_TIMER1:
- case WCD938X_HPH_NEW_INT_HPH_TIMER2:
- case WCD938X_HPH_NEW_INT_HPH_TIMER3:
- case WCD938X_HPH_NEW_INT_HPH_TIMER4:
- case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2:
- case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3:
- case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW:
- case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW:
- case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI:
- case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP:
- case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP:
- case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL:
- case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL:
- case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT:
- case WCD938X_MBHC_NEW_INT_SPARE_2:
- case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON:
- case WCD938X_EAR_INT_NEW_CNP_VCM_CON1:
- case WCD938X_EAR_INT_NEW_CNP_VCM_CON2:
- case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS:
- case WCD938X_AUX_INT_EN_REG:
- case WCD938X_AUX_INT_PA_CTRL:
- case WCD938X_AUX_INT_SP_CTRL:
- case WCD938X_AUX_INT_DAC_CTRL:
- case WCD938X_AUX_INT_CLK_CTRL:
- case WCD938X_AUX_INT_TEST_CTRL:
- case WCD938X_AUX_INT_MISC:
- case WCD938X_LDORXTX_INT_BIAS:
- case WCD938X_LDORXTX_INT_STB_LOADS_DTEST:
- case WCD938X_LDORXTX_INT_TEST0:
- case WCD938X_LDORXTX_INT_STARTUP_TIMER:
- case WCD938X_LDORXTX_INT_TEST1:
- case WCD938X_SLEEP_INT_WATCHDOG_CTL_1:
- case WCD938X_SLEEP_INT_WATCHDOG_CTL_2:
- case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1:
- case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2:
- case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2:
- case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1:
- case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0:
- case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M:
- case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M:
- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1:
- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0:
- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP:
- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1:
- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0:
- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP:
- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0:
- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP:
- case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1:
- case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP:
- case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2:
- case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1:
- case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0:
- case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP:
- case WCD938X_DIGITAL_PAGE_REGISTER:
- case WCD938X_DIGITAL_SWR_TX_CLK_RATE:
- case WCD938X_DIGITAL_CDC_RST_CTL:
- case WCD938X_DIGITAL_TOP_CLK_CFG:
- case WCD938X_DIGITAL_CDC_ANA_CLK_CTL:
- case WCD938X_DIGITAL_CDC_DIG_CLK_CTL:
- case WCD938X_DIGITAL_SWR_RST_EN:
- case WCD938X_DIGITAL_CDC_PATH_MODE:
- case WCD938X_DIGITAL_CDC_RX_RST:
- case WCD938X_DIGITAL_CDC_RX0_CTL:
- case WCD938X_DIGITAL_CDC_RX1_CTL:
- case WCD938X_DIGITAL_CDC_RX2_CTL:
- case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1:
- case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3:
- case WCD938X_DIGITAL_CDC_COMP_CTL_0:
- case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0:
- case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0:
- case WCD938X_DIGITAL_CDC_HPH_DSM_C_0:
- case WCD938X_DIGITAL_CDC_HPH_DSM_C_1:
- case WCD938X_DIGITAL_CDC_HPH_DSM_C_2:
- case WCD938X_DIGITAL_CDC_HPH_DSM_C_3:
- case WCD938X_DIGITAL_CDC_HPH_DSM_R1:
- case WCD938X_DIGITAL_CDC_HPH_DSM_R2:
- case WCD938X_DIGITAL_CDC_HPH_DSM_R3:
- case WCD938X_DIGITAL_CDC_HPH_DSM_R4:
- case WCD938X_DIGITAL_CDC_HPH_DSM_R5:
- case WCD938X_DIGITAL_CDC_HPH_DSM_R6:
- case WCD938X_DIGITAL_CDC_HPH_DSM_R7:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0:
- case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0:
- case WCD938X_DIGITAL_CDC_AUX_DSM_C_0:
- case WCD938X_DIGITAL_CDC_AUX_DSM_C_1:
- case WCD938X_DIGITAL_CDC_AUX_DSM_C_2:
- case WCD938X_DIGITAL_CDC_AUX_DSM_C_3:
- case WCD938X_DIGITAL_CDC_AUX_DSM_R1:
- case WCD938X_DIGITAL_CDC_AUX_DSM_R2:
- case WCD938X_DIGITAL_CDC_AUX_DSM_R3:
- case WCD938X_DIGITAL_CDC_AUX_DSM_R4:
- case WCD938X_DIGITAL_CDC_AUX_DSM_R5:
- case WCD938X_DIGITAL_CDC_AUX_DSM_R6:
- case WCD938X_DIGITAL_CDC_AUX_DSM_R7:
- case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0:
- case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1:
- case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0:
- case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1:
- case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2:
- case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0:
- case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1:
- case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2:
- case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL:
- case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL:
- case WCD938X_DIGITAL_CDC_EAR_PATH_CTL:
- case WCD938X_DIGITAL_CDC_SWR_CLH:
- case WCD938X_DIGITAL_SWR_CLH_BYP:
- case WCD938X_DIGITAL_CDC_TX0_CTL:
- case WCD938X_DIGITAL_CDC_TX1_CTL:
- case WCD938X_DIGITAL_CDC_TX2_CTL:
- case WCD938X_DIGITAL_CDC_TX_RST:
- case WCD938X_DIGITAL_CDC_REQ_CTL:
- case WCD938X_DIGITAL_CDC_RST:
- case WCD938X_DIGITAL_CDC_AMIC_CTL:
- case WCD938X_DIGITAL_CDC_DMIC_CTL:
- case WCD938X_DIGITAL_CDC_DMIC1_CTL:
- case WCD938X_DIGITAL_CDC_DMIC2_CTL:
- case WCD938X_DIGITAL_CDC_DMIC3_CTL:
- case WCD938X_DIGITAL_CDC_DMIC4_CTL:
- case WCD938X_DIGITAL_EFUSE_PRG_CTL:
- case WCD938X_DIGITAL_EFUSE_CTL:
- case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2:
- case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4:
- case WCD938X_DIGITAL_PDM_WD_CTL0:
- case WCD938X_DIGITAL_PDM_WD_CTL1:
- case WCD938X_DIGITAL_PDM_WD_CTL2:
- case WCD938X_DIGITAL_INTR_MODE:
- case WCD938X_DIGITAL_INTR_MASK_0:
- case WCD938X_DIGITAL_INTR_MASK_1:
- case WCD938X_DIGITAL_INTR_MASK_2:
- case WCD938X_DIGITAL_INTR_CLEAR_0:
- case WCD938X_DIGITAL_INTR_CLEAR_1:
- case WCD938X_DIGITAL_INTR_CLEAR_2:
- case WCD938X_DIGITAL_INTR_LEVEL_0:
- case WCD938X_DIGITAL_INTR_LEVEL_1:
- case WCD938X_DIGITAL_INTR_LEVEL_2:
- case WCD938X_DIGITAL_INTR_SET_0:
- case WCD938X_DIGITAL_INTR_SET_1:
- case WCD938X_DIGITAL_INTR_SET_2:
- case WCD938X_DIGITAL_INTR_TEST_0:
- case WCD938X_DIGITAL_INTR_TEST_1:
- case WCD938X_DIGITAL_INTR_TEST_2:
- case WCD938X_DIGITAL_TX_MODE_DBG_EN:
- case WCD938X_DIGITAL_TX_MODE_DBG_0_1:
- case WCD938X_DIGITAL_TX_MODE_DBG_2_3:
- case WCD938X_DIGITAL_LB_IN_SEL_CTL:
- case WCD938X_DIGITAL_LOOP_BACK_MODE:
- case WCD938X_DIGITAL_SWR_DAC_TEST:
- case WCD938X_DIGITAL_SWR_HM_TEST_RX_0:
- case WCD938X_DIGITAL_SWR_HM_TEST_TX_0:
- case WCD938X_DIGITAL_SWR_HM_TEST_RX_1:
- case WCD938X_DIGITAL_SWR_HM_TEST_TX_1:
- case WCD938X_DIGITAL_SWR_HM_TEST_TX_2:
- case WCD938X_DIGITAL_PAD_CTL_SWR_0:
- case WCD938X_DIGITAL_PAD_CTL_SWR_1:
- case WCD938X_DIGITAL_I2C_CTL:
- case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE:
- case WCD938X_DIGITAL_EFUSE_TEST_CTL_0:
- case WCD938X_DIGITAL_EFUSE_TEST_CTL_1:
- case WCD938X_DIGITAL_PAD_CTL_PDM_RX0:
- case WCD938X_DIGITAL_PAD_CTL_PDM_RX1:
- case WCD938X_DIGITAL_PAD_CTL_PDM_TX0:
- case WCD938X_DIGITAL_PAD_CTL_PDM_TX1:
- case WCD938X_DIGITAL_PAD_CTL_PDM_TX2:
- case WCD938X_DIGITAL_PAD_INP_DIS_0:
- case WCD938X_DIGITAL_PAD_INP_DIS_1:
- case WCD938X_DIGITAL_DRIVE_STRENGTH_0:
- case WCD938X_DIGITAL_DRIVE_STRENGTH_1:
- case WCD938X_DIGITAL_DRIVE_STRENGTH_2:
- case WCD938X_DIGITAL_RX_DATA_EDGE_CTL:
- case WCD938X_DIGITAL_TX_DATA_EDGE_CTL:
- case WCD938X_DIGITAL_GPIO_MODE:
- case WCD938X_DIGITAL_PIN_CTL_OE:
- case WCD938X_DIGITAL_PIN_CTL_DATA_0:
- case WCD938X_DIGITAL_PIN_CTL_DATA_1:
- case WCD938X_DIGITAL_DIG_DEBUG_CTL:
- case WCD938X_DIGITAL_DIG_DEBUG_EN:
- case WCD938X_DIGITAL_ANA_CSR_DBG_ADD:
- case WCD938X_DIGITAL_ANA_CSR_DBG_CTL:
- case WCD938X_DIGITAL_SSP_DBG:
- case WCD938X_DIGITAL_SPARE_0:
- case WCD938X_DIGITAL_SPARE_1:
- case WCD938X_DIGITAL_SPARE_2:
- case WCD938X_DIGITAL_TX_REQ_FB_CTL_0:
- case WCD938X_DIGITAL_TX_REQ_FB_CTL_1:
- case WCD938X_DIGITAL_TX_REQ_FB_CTL_2:
- case WCD938X_DIGITAL_TX_REQ_FB_CTL_3:
- case WCD938X_DIGITAL_TX_REQ_FB_CTL_4:
- case WCD938X_DIGITAL_DEM_BYPASS_DATA0:
- case WCD938X_DIGITAL_DEM_BYPASS_DATA1:
- case WCD938X_DIGITAL_DEM_BYPASS_DATA2:
- case WCD938X_DIGITAL_DEM_BYPASS_DATA3:
- return true;
- }
-
- return false;
-}
-
-static bool wcd938x_readonly_register(struct device *dev, unsigned int reg)
-{
- switch (reg) {
- case WCD938X_ANA_MBHC_RESULT_1:
- case WCD938X_ANA_MBHC_RESULT_2:
- case WCD938X_ANA_MBHC_RESULT_3:
- case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS:
- case WCD938X_TX_1_2_SAR2_ERR:
- case WCD938X_TX_1_2_SAR1_ERR:
- case WCD938X_TX_3_4_SAR4_ERR:
- case WCD938X_TX_3_4_SAR3_ERR:
- case WCD938X_HPH_L_STATUS:
- case WCD938X_HPH_R_STATUS:
- case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS:
- case WCD938X_EAR_STATUS_REG_1:
- case WCD938X_EAR_STATUS_REG_2:
- case WCD938X_MBHC_NEW_FSM_STATUS:
- case WCD938X_MBHC_NEW_ADC_RESULT:
- case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT:
- case WCD938X_AUX_INT_STATUS_REG:
- case WCD938X_LDORXTX_INT_STATUS:
- case WCD938X_DIGITAL_CHIP_ID0:
- case WCD938X_DIGITAL_CHIP_ID1:
- case WCD938X_DIGITAL_CHIP_ID2:
- case WCD938X_DIGITAL_CHIP_ID3:
- case WCD938X_DIGITAL_INTR_STATUS_0:
- case WCD938X_DIGITAL_INTR_STATUS_1:
- case WCD938X_DIGITAL_INTR_STATUS_2:
- case WCD938X_DIGITAL_INTR_CLEAR_0:
- case WCD938X_DIGITAL_INTR_CLEAR_1:
- case WCD938X_DIGITAL_INTR_CLEAR_2:
- case WCD938X_DIGITAL_SWR_HM_TEST_0:
- case WCD938X_DIGITAL_SWR_HM_TEST_1:
- case WCD938X_DIGITAL_EFUSE_T_DATA_0:
- case WCD938X_DIGITAL_EFUSE_T_DATA_1:
- case WCD938X_DIGITAL_PIN_STATUS_0:
- case WCD938X_DIGITAL_PIN_STATUS_1:
- case WCD938X_DIGITAL_MODE_STATUS_0:
- case WCD938X_DIGITAL_MODE_STATUS_1:
- case WCD938X_DIGITAL_EFUSE_REG_0:
- case WCD938X_DIGITAL_EFUSE_REG_1:
- case WCD938X_DIGITAL_EFUSE_REG_2:
- case WCD938X_DIGITAL_EFUSE_REG_3:
- case WCD938X_DIGITAL_EFUSE_REG_4:
- case WCD938X_DIGITAL_EFUSE_REG_5:
- case WCD938X_DIGITAL_EFUSE_REG_6:
- case WCD938X_DIGITAL_EFUSE_REG_7:
- case WCD938X_DIGITAL_EFUSE_REG_8:
- case WCD938X_DIGITAL_EFUSE_REG_9:
- case WCD938X_DIGITAL_EFUSE_REG_10:
- case WCD938X_DIGITAL_EFUSE_REG_11:
- case WCD938X_DIGITAL_EFUSE_REG_12:
- case WCD938X_DIGITAL_EFUSE_REG_13:
- case WCD938X_DIGITAL_EFUSE_REG_14:
- case WCD938X_DIGITAL_EFUSE_REG_15:
- case WCD938X_DIGITAL_EFUSE_REG_16:
- case WCD938X_DIGITAL_EFUSE_REG_17:
- case WCD938X_DIGITAL_EFUSE_REG_18:
- case WCD938X_DIGITAL_EFUSE_REG_19:
- case WCD938X_DIGITAL_EFUSE_REG_20:
- case WCD938X_DIGITAL_EFUSE_REG_21:
- case WCD938X_DIGITAL_EFUSE_REG_22:
- case WCD938X_DIGITAL_EFUSE_REG_23:
- case WCD938X_DIGITAL_EFUSE_REG_24:
- case WCD938X_DIGITAL_EFUSE_REG_25:
- case WCD938X_DIGITAL_EFUSE_REG_26:
- case WCD938X_DIGITAL_EFUSE_REG_27:
- case WCD938X_DIGITAL_EFUSE_REG_28:
- case WCD938X_DIGITAL_EFUSE_REG_29:
- case WCD938X_DIGITAL_EFUSE_REG_30:
- case WCD938X_DIGITAL_EFUSE_REG_31:
- return true;
- }
- return false;
-}
-
-static bool wcd938x_readable_register(struct device *dev, unsigned int reg)
-{
- bool ret;
-
- ret = wcd938x_readonly_register(dev, reg);
- if (!ret)
- return wcd938x_rdwr_register(dev, reg);
-
- return ret;
-}
-
-static bool wcd938x_writeable_register(struct device *dev, unsigned int reg)
-{
- return wcd938x_rdwr_register(dev, reg);
-}
-
-static bool wcd938x_volatile_register(struct device *dev, unsigned int reg)
-{
- if (reg <= WCD938X_BASE_ADDRESS)
- return false;
-
- if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE)
- return true;
-
- if (wcd938x_readonly_register(dev, reg))
- return true;
-
- return false;
-}
-
-static struct regmap_config wcd938x_regmap_config = {
- .name = "wcd938x_csr",
- .reg_bits = 32,
- .val_bits = 8,
- .cache_type = REGCACHE_RBTREE,
- .reg_defaults = wcd938x_defaults,
- .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults),
- .max_register = WCD938X_MAX_REGISTER,
- .readable_reg = wcd938x_readable_register,
- .writeable_reg = wcd938x_writeable_register,
- .volatile_reg = wcd938x_volatile_register,
- .can_multi_write = true,
-};
-
static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
@@ -4412,10 +3417,10 @@ static int wcd938x_bind(struct device *dev)
return -EINVAL;
}
- wcd938x->regmap = devm_regmap_init_sdw(wcd938x->tx_sdw_dev, &wcd938x_regmap_config);
- if (IS_ERR(wcd938x->regmap)) {
- dev_err(dev, "%s: tx csr regmap not found\n", __func__);
- return PTR_ERR(wcd938x->regmap);
+ wcd938x->regmap = dev_get_regmap(&wcd938x->tx_sdw_dev->dev, NULL);
+ if (!wcd938x->regmap) {
+ dev_err(dev, "could not get TX device regmap\n");
+ return -EINVAL;
}
ret = wcd938x_irq_init(wcd938x, dev);
diff --git a/sound/soc/codecs/wcd938x.h b/sound/soc/codecs/wcd938x.h
index ea82039e7843..74b1498fec38 100644
--- a/sound/soc/codecs/wcd938x.h
+++ b/sound/soc/codecs/wcd938x.h
@@ -663,6 +663,7 @@ struct wcd938x_sdw_priv {
bool is_tx;
struct wcd938x_priv *wcd938x;
struct irq_domain *slave_irq;
+ struct regmap *regmap;
};
#if IS_ENABLED(CONFIG_SND_SOC_WCD938X_SDW)
diff --git a/sound/soc/codecs/wsa881x.c b/sound/soc/codecs/wsa881x.c
index 6c8b1db649b8..046843b57b03 100644
--- a/sound/soc/codecs/wsa881x.c
+++ b/sound/soc/codecs/wsa881x.c
@@ -1101,7 +1101,7 @@ static int wsa881x_bus_config(struct sdw_slave *slave,
return 0;
}
-static struct sdw_slave_ops wsa881x_slave_ops = {
+static const struct sdw_slave_ops wsa881x_slave_ops = {
.update_status = wsa881x_update_status,
.bus_config = wsa881x_bus_config,
.port_prep = wsa881x_port_prep,
diff --git a/sound/soc/codecs/wsa883x.c b/sound/soc/codecs/wsa883x.c
index 2533d0973529..6e9a64c5948e 100644
--- a/sound/soc/codecs/wsa883x.c
+++ b/sound/soc/codecs/wsa883x.c
@@ -1073,7 +1073,7 @@ static int wsa883x_port_prep(struct sdw_slave *slave,
return 0;
}
-static struct sdw_slave_ops wsa883x_slave_ops = {
+static const struct sdw_slave_ops wsa883x_slave_ops = {
.update_status = wsa883x_update_status,
.port_prep = wsa883x_port_prep,
};
diff --git a/sound/soc/intel/common/soc-acpi-intel-byt-match.c b/sound/soc/intel/common/soc-acpi-intel-byt-match.c
index db5a92b9875a..87c44f284971 100644
--- a/sound/soc/intel/common/soc-acpi-intel-byt-match.c
+++ b/sound/soc/intel/common/soc-acpi-intel-byt-match.c
@@ -124,7 +124,7 @@ static const struct snd_soc_acpi_codecs rt5640_comp_ids = {
};
static const struct snd_soc_acpi_codecs wm5102_comp_ids = {
- .num_codecs = 2,
+ .num_codecs = 3,
.codecs = { "10WM5102", "WM510204", "WM510205"},
};
diff --git a/sound/usb/caiaq/input.c b/sound/usb/caiaq/input.c
index 1e2cf2f08eec..84f26dce7f5d 100644
--- a/sound/usb/caiaq/input.c
+++ b/sound/usb/caiaq/input.c
@@ -804,6 +804,7 @@ int snd_usb_caiaq_input_init(struct snd_usb_caiaqdev *cdev)
default:
/* no input methods supported on this device */
+ ret = -EINVAL;
goto exit_free_idev;
}
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