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* HEVC: Set the default flat IQ matrixXiang, Haihao2014-12-141-0/+1
| | | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit d76ba3c5d46878be134dcdf1c17bb1a4e7f276f2)
* HEVC: All internal buffers used for HCP pipe on SKLXiang, Haihao2014-12-141-0/+17
| | | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit fb48bc409a187ad1bc8a4ef626d95c4ecfaff828)
* decoder: h264: fix frame store logic for MVC.Gwenole Beauchesne2014-06-161-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In strict MVC decoding mode, when only the necessary set of inter-view reference pictures are passed to the ReferenceFrames array for decoding the current picture, we should not re-use a frame store id that might be needed for decoding another view component in the same access unit. One way to solve this problem is to track when the VA surface in a specified frame store id was last referenced. So, a "ref_age" field is introduced to the GenFrameStore struct and is updated whenever the surface is being referenced. Additionally, the list of retired refs candidates (free_refs) is kept ordered by increasing ref_age. That way, we can immediately know what is the oldest frame store id to recycle. Let deltaAge = CurrAge - RefAge: If deltaAge > 1, we know for sure that the VA surface is gone ; If deltaAge = 1, the surface could be re-used for inter prediction ; If deltaAge = 0, the surface could be re-used for inter-view prediction. The ref_age in each Frame Store entry is always current, i.e. it is the same for all reference frames that intervened in the decoding process of all inter view components of the previous access unit. The age tracks access units. v2: used a more correct representation of age, instead of POC [Yakui] v3: minor optimization for detecting changes of access unit [Haihao] Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> (cherry picked from commit 3b5eb0522fbfe1220dcd0c0bb093a93cfc25e22c)
* Update states for VP8 decoding on BDWXiang, Haihao2014-02-271-0/+1
| | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
* Add the separated media encoding/decoding files for BDWZhao Yakui2014-02-271-0/+2
| | | | | | | | | | As a lot of changes about the media are added between Haswell and BDW, the separated media encoding/decoding files are added for BDW. This is to avoid complex backward logic for Haswell. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> [Haihao: directly use object instead of id] Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
* Merge branch 'master' into stagingXiang, Haihao2013-04-031-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: NEWS configure.ac src/Makefile.am src/gen6_mfc.c src/gen6_mfd.c src/gen6_vme.c src/gen6_vme.h src/gen75_mfc.c src/gen75_mfd.c src/gen75_vme.c src/gen75_vpp_vebox.c src/gen75_vpp_vebox.h src/gen7_mfd.c src/i965_avc_bsd.c src/i965_decoder.h src/i965_decoder_utils.c src/i965_defines.h src/i965_drv_video.c src/i965_drv_video.h src/i965_encoder.c src/i965_encoder.h src/i965_output_dri.c src/i965_post_processing.c src/i965_post_processing.h src/i965_render.c src/i965_structs.h src/intel_driver.c src/object_heap.c src/shaders/post_processing/Common/AYUV_Load_16x8.asm src/shaders/post_processing/Common/AYUV_Load_16x8.inc src/shaders/post_processing/Common/Init_All_Regs.asm src/shaders/post_processing/Makefile.am src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc src/shaders/post_processing/gen5_6/Makefile.am src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b src/shaders/post_processing/gen7/EOT.g4a src/shaders/post_processing/gen7/Makefile.am src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a src/shaders/post_processing/gen7/Save_AVS_NV12.g4a src/shaders/post_processing/gen7/Save_AVS_PA.g4a src/shaders/post_processing/gen7/Save_AVS_PL3.g4a src/shaders/post_processing/gen7/Save_AVS_RGB.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a src/shaders/post_processing/gen7/Set_Layer_0.g4a src/shaders/post_processing/gen7/VP_Setup.g4a src/shaders/vme/Makefile.am src/shaders/vme/inter_frame_haswell.asm src/shaders/vme/inter_frame_haswell.g75b src/shaders/vme/intra_frame_haswell.asm src/shaders/vme/intra_frame_haswell.g75b src/shaders/vme/vme75.inc src/shaders/vme/vme7_mpeg2.inc
| * Fix thread issue with AVC private surafceGautam2012-10-241-2/+13
| | | | | | | | | | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=55282 Signed-off-by: Gautam <manamgautam@gmail.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
| * Unify the code for xxx_free_avc_surfaceXiang, Haihao2012-10-241-0/+31
| | | | | | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
| * Add the seperated file for media decoding on HaswellZhao Yakui2012-10-231-0/+3
| | | | | | | | | | | | | | | | As the MFX involves quite a lot of changes between Ivy and Haswell, the seperated file is added for the media decoding on haswell. This can avoid the complex backward logic for Ivy. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
* | Decoder: directly use surface object for decodingXiang, Haihao2013-03-151-0/+1
| | | | | | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
* | Unify the XXX_free_avc_surface for media encoding/decodingZhao Yakui2012-10-311-39/+0
| | | | | | | | Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
* | Fix thread issue with AVC private surafceGautam2012-10-311-2/+13
| | | | | | | | | | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=55282 Signed-off-by: Gautam <manamgautam@gmail.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
* | Unify the code for xxx_free_avc_surfaceXiang, Haihao2012-10-311-0/+31
| | | | | | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
* | Add the seperate decoding callback API for HaswellZhao Yakui2012-10-231-0/+3
|/ | | | | | | | As the MFX involves quite a lot of changes between Ivy and Haswell, the seperate decoding callback API is added for haswell. This can avoid the complex backward logic for Ivy. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
* Factor out type definitions (GenFrameStore, GenBuffer).Gwenole Beauchesne2012-02-011-0/+46
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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