diff options
-rw-r--r-- | src/gen6_mfc.c | 4 | ||||
-rw-r--r-- | src/gen6_mfc.h | 36 | ||||
-rw-r--r-- | src/gen6_mfc_common.c | 636 | ||||
-rw-r--r-- | src/gen6_vme.c | 62 | ||||
-rw-r--r-- | src/gen6_vme.h | 46 | ||||
-rw-r--r-- | src/gen75_mfc.c | 524 | ||||
-rw-r--r-- | src/gen75_vme.c | 110 | ||||
-rw-r--r-- | src/gen7_mfc.c | 214 | ||||
-rw-r--r-- | src/gen7_vme.c | 256 |
9 files changed, 944 insertions, 944 deletions
diff --git a/src/gen6_mfc.c b/src/gen6_mfc.c index 1103e612..62fa2e93 100644 --- a/src/gen6_mfc.c +++ b/src/gen6_mfc.c @@ -609,8 +609,8 @@ gen6_mfc_init(VADriverContextP ctx, } static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; diff --git a/src/gen6_mfc.h b/src/gen6_mfc.h index e6b04a16..1b71218a 100644 --- a/src/gen6_mfc.h +++ b/src/gen6_mfc.h @@ -200,10 +200,10 @@ struct gen6_mfc_context void (*set_surface_state)(VADriverContextP ctx, struct intel_encoder_context *encoder_context); void (*ind_obj_base_addr_state)(VADriverContextP ctx, - struct intel_encoder_context *encoder_context); + struct intel_encoder_context *encoder_context); void (*avc_img_state)(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context); + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context); void (*avc_qm_state)(VADriverContextP ctx, struct intel_encoder_context *encoder_context); void (*avc_fqm_state)(VADriverContextP ctx, @@ -234,38 +234,38 @@ Bool gen75_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context * extern int intel_mfc_update_hrd(struct encode_state *encode_state, - struct gen6_mfc_context *mfc_context, - int frame_bits); + struct gen6_mfc_context *mfc_context, + int frame_bits); extern int intel_mfc_brc_postpack(struct encode_state *encode_state, - struct gen6_mfc_context *mfc_context, - int frame_bits); + struct gen6_mfc_context *mfc_context, + int frame_bits); extern void intel_mfc_hrd_context_update(struct encode_state *encode_state, - struct gen6_mfc_context *mfc_context); + struct gen6_mfc_context *mfc_context); extern int intel_mfc_interlace_check(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context); + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context); extern void intel_mfc_brc_prepare(struct encode_state *encode_state, - struct intel_encoder_context *encoder_context); + struct intel_encoder_context *encoder_context); extern void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - struct intel_batchbuffer *slice_batch); + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + struct intel_batchbuffer *slice_batch); extern VAStatus intel_mfc_avc_prepare(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context); + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context); extern int intel_avc_enc_slice_type_fixup(int type); extern void intel_mfc_avc_ref_idx_state(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context); + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context); #endif /* _GEN6_MFC_BCS_H_ */ diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c index 469bf640..88a8d618 100644 --- a/src/gen6_mfc_common.c +++ b/src/gen6_mfc_common.c @@ -43,10 +43,10 @@ #include "gen6_vme.h" #include "intel_media.h" -#define BRC_CLIP(x, min, max) \ -{ \ - x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x)); \ -} +#define BRC_CLIP(x, min, max) \ + { \ + x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x)); \ + } #define BRC_P_B_QP_DIFF 4 #define BRC_I_P_QP_DIFF 2 @@ -86,7 +86,7 @@ int intel_avc_enc_slice_type_fixup(int slice_type) static void intel_mfc_bit_rate_control_context_init(struct encode_state *encode_state, - struct gen6_mfc_context *mfc_context) + struct gen6_mfc_context *mfc_context) { VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; @@ -130,7 +130,7 @@ intel_mfc_bit_rate_control_context_init(struct encode_state *encode_state, } static void intel_mfc_brc_init(struct encode_state *encode_state, - struct intel_encoder_context* encoder_context) + struct intel_encoder_context* encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; @@ -166,7 +166,7 @@ static void intel_mfc_brc_init(struct encode_state *encode_state, mfc_context->hrd.buffer_size = (double)pParameterHRD->buffer_size; mfc_context->hrd.current_buffer_fullness = (double)(pParameterHRD->initial_buffer_fullness < mfc_context->hrd.buffer_size)? - pParameterHRD->initial_buffer_fullness: mfc_context->hrd.buffer_size/2.; + pParameterHRD->initial_buffer_fullness: mfc_context->hrd.buffer_size/2.; mfc_context->hrd.target_buffer_fullness = (double)mfc_context->hrd.buffer_size/2.; mfc_context->hrd.buffer_capacity = (double)mfc_context->hrd.buffer_size/qp1_size; mfc_context->hrd.violation_noted = 0; @@ -188,8 +188,8 @@ static void intel_mfc_brc_init(struct encode_state *encode_state, } int intel_mfc_update_hrd(struct encode_state *encode_state, - struct gen6_mfc_context *mfc_context, - int frame_bits) + struct gen6_mfc_context *mfc_context, + int frame_bits) { double prev_bf = mfc_context->hrd.current_buffer_fullness; @@ -213,8 +213,8 @@ int intel_mfc_update_hrd(struct encode_state *encode_state, } int intel_mfc_brc_postpack(struct encode_state *encode_state, - struct gen6_mfc_context *mfc_context, - int frame_bits) + struct gen6_mfc_context *mfc_context, + int frame_bits) { gen6_brc_status sts = BRC_NO_HRD_VIOLATION; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; @@ -243,7 +243,7 @@ int intel_mfc_brc_postpack(struct encode_state *encode_state, frame_size_alpha = (double)mfc_context->brc.gop_nums[slicetype]; if (frame_size_alpha > 30) frame_size_alpha = 30; frame_size_next = target_frame_size + (double)(target_frame_size - frame_bits) / - (double)(frame_size_alpha + 1.); + (double)(frame_size_alpha + 1.); /* frame_size_next: avoiding negative number and too small value */ if ((double)frame_size_next < (double)(target_frame_size * 0.25)) @@ -333,7 +333,7 @@ int intel_mfc_brc_postpack(struct encode_state *encode_state, } static void intel_mfc_hrd_context_init(struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; @@ -357,14 +357,14 @@ static void intel_mfc_hrd_context_init(struct encode_state *encode_state, void intel_mfc_hrd_context_update(struct encode_state *encode_state, - struct gen6_mfc_context *mfc_context) + struct gen6_mfc_context *mfc_context) { mfc_context->vui_hrd.i_frame_number++; } int intel_mfc_interlace_check(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSliceParameterBufferH264 *pSliceParameter; @@ -385,7 +385,7 @@ int intel_mfc_interlace_check(VADriverContextP ctx, } void intel_mfc_brc_prepare(struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct intel_encoder_context *encoder_context) { unsigned int rate_control_mode = encoder_context->rate_control_mode; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -404,9 +404,9 @@ void intel_mfc_brc_prepare(struct encode_state *encode_state, } void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - struct intel_batchbuffer *slice_batch) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + struct intel_batchbuffer *slice_batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SPS); @@ -484,13 +484,13 @@ void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx, unsigned char *sei_data = NULL; int length_in_bits = build_avc_sei_buffer_timing( - mfc_context->vui_hrd.i_initial_cpb_removal_delay_length, - mfc_context->vui_hrd.i_initial_cpb_removal_delay, - 0, - mfc_context->vui_hrd.i_cpb_removal_delay_length, mfc_context->vui_hrd.i_cpb_removal_delay * mfc_context->vui_hrd.i_frame_number, - mfc_context->vui_hrd.i_dpb_output_delay_length, - 0, - &sei_data); + mfc_context->vui_hrd.i_initial_cpb_removal_delay_length, + mfc_context->vui_hrd.i_initial_cpb_removal_delay, + 0, + mfc_context->vui_hrd.i_cpb_removal_delay_length, mfc_context->vui_hrd.i_cpb_removal_delay * mfc_context->vui_hrd.i_frame_number, + mfc_context->vui_hrd.i_dpb_output_delay_length, + 0, + &sei_data); mfc_context->insert_object(ctx, encoder_context, (unsigned int *)sei_data, @@ -506,8 +506,8 @@ void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx, } VAStatus intel_mfc_avc_prepare(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -662,44 +662,44 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx, */ int intel_format_lutvalue(int value, int max) { - int ret; - int logvalue, temp1, temp2; + int ret; + int logvalue, temp1, temp2; - if (value <= 0) - return 0; + if (value <= 0) + return 0; - logvalue = (int)(log2f((float)value)); - if (logvalue < 4) { - ret = value; - } else { - int error, temp_value, base, j, temp_err; - error = value; - j = logvalue - 4 + 1; - ret = -1; - for(; j <= logvalue; j++) { - if (j == 0) { - base = value >> j; - } else { - base = (value + (1 << (j - 1)) - 1) >> j; - } - if (base >= 16) - continue; - - temp_value = base << j; - temp_err = abs(value - temp_value); - if (temp_err < error) { - error = temp_err; - ret = (j << 4) | base; - if (temp_err == 0) - break; - } - } - } - temp1 = (ret & 0xf) << ((ret & 0xf0) >> 4); - temp2 = (max & 0xf) << ((max & 0xf0) >> 4); - if (temp1 > temp2) - ret = max; - return ret; + logvalue = (int)(log2f((float)value)); + if (logvalue < 4) { + ret = value; + } else { + int error, temp_value, base, j, temp_err; + error = value; + j = logvalue - 4 + 1; + ret = -1; + for(; j <= logvalue; j++) { + if (j == 0) { + base = value >> j; + } else { + base = (value + (1 << (j - 1)) - 1) >> j; + } + if (base >= 16) + continue; + + temp_value = base << j; + temp_err = abs(value - temp_value); + if (temp_err < error) { + error = temp_err; + ret = (j << 4) | base; + if (temp_err == 0) + break; + } + } + } + temp1 = (ret & 0xf) << ((ret & 0xf0) >> 4); + temp2 = (max & 0xf) << ((max & 0xf0) >> 4); + if (temp1 > temp2) + ret = max; + return ret; } @@ -709,19 +709,19 @@ int intel_format_lutvalue(int value, int max) static float intel_lambda_qp(int qp) { - float value, lambdaf; - value = qp; - value = value / 6 - 2; - if (value < 0) - value = 0; - lambdaf = roundf(powf(2, value)); - return lambdaf; + float value, lambdaf; + value = qp; + value = value / 6 - 2; + if (value < 0) + value = 0; + lambdaf = roundf(powf(2, value)); + return lambdaf; } void intel_vme_update_mbmv_cost(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; @@ -756,30 +756,30 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx, m_cost = 0; vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f); for (j = 1; j < 3; j++) { - m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; - m_cost = (int)m_costf; - vme_state_message[MODE_INTER_MV0 + j] = intel_format_lutvalue(m_cost, 0x6f); + m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; + m_cost = (int)m_costf; + vme_state_message[MODE_INTER_MV0 + j] = intel_format_lutvalue(m_cost, 0x6f); } mv_count = 3; for (j = 4; j <= 64; j *= 2) { - m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; - m_cost = (int)m_costf; - vme_state_message[MODE_INTER_MV0 + mv_count] = intel_format_lutvalue(m_cost, 0x6f); - mv_count++; + m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; + m_cost = (int)m_costf; + vme_state_message[MODE_INTER_MV0 + mv_count] = intel_format_lutvalue(m_cost, 0x6f); + mv_count++; } if (qp <= 25) { - vme_state_message[MODE_INTRA_16X16] = 0x4a; - vme_state_message[MODE_INTRA_8X8] = 0x4a; - vme_state_message[MODE_INTRA_4X4] = 0x4a; - vme_state_message[MODE_INTRA_NONPRED] = 0x4a; - vme_state_message[MODE_INTER_16X16] = 0x4a; - vme_state_message[MODE_INTER_16X8] = 0x4a; - vme_state_message[MODE_INTER_8X8] = 0x4a; - vme_state_message[MODE_INTER_8X4] = 0x4a; - vme_state_message[MODE_INTER_4X4] = 0x4a; - vme_state_message[MODE_INTER_BWD] = 0x2a; - return; + vme_state_message[MODE_INTRA_16X16] = 0x4a; + vme_state_message[MODE_INTRA_8X8] = 0x4a; + vme_state_message[MODE_INTRA_4X4] = 0x4a; + vme_state_message[MODE_INTRA_NONPRED] = 0x4a; + vme_state_message[MODE_INTER_16X16] = 0x4a; + vme_state_message[MODE_INTER_16X8] = 0x4a; + vme_state_message[MODE_INTER_8X8] = 0x4a; + vme_state_message[MODE_INTER_8X4] = 0x4a; + vme_state_message[MODE_INTER_4X4] = 0x4a; + vme_state_message[MODE_INTER_BWD] = 0x2a; + return; } m_costf = lambda * 10; vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost, 0x8f); @@ -791,42 +791,42 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx, m_cost = m_costf; vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost, 0x6f); if (slice_type == SLICE_TYPE_P) { - m_costf = lambda * 2.5; - m_cost = m_costf; - vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f); - m_costf = lambda * 4; - m_cost = m_costf; - vme_state_message[MODE_INTER_16X8] = intel_format_lutvalue(m_cost, 0x8f); - m_costf = lambda * 1.5; - m_cost = m_costf; - vme_state_message[MODE_INTER_8X8] = intel_format_lutvalue(m_cost, 0x6f); - m_costf = lambda * 3; - m_cost = m_costf; - vme_state_message[MODE_INTER_8X4] = intel_format_lutvalue(m_cost, 0x6f); - m_costf = lambda * 5; - m_cost = m_costf; - vme_state_message[MODE_INTER_4X4] = intel_format_lutvalue(m_cost, 0x6f); - /* BWD is not used in P-frame */ - vme_state_message[MODE_INTER_BWD] = 0; + m_costf = lambda * 2.5; + m_cost = m_costf; + vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f); + m_costf = lambda * 4; + m_cost = m_costf; + vme_state_message[MODE_INTER_16X8] = intel_format_lutvalue(m_cost, 0x8f); + m_costf = lambda * 1.5; + m_cost = m_costf; + vme_state_message[MODE_INTER_8X8] = intel_format_lutvalue(m_cost, 0x6f); + m_costf = lambda * 3; + m_cost = m_costf; + vme_state_message[MODE_INTER_8X4] = intel_format_lutvalue(m_cost, 0x6f); + m_costf = lambda * 5; + m_cost = m_costf; + vme_state_message[MODE_INTER_4X4] = intel_format_lutvalue(m_cost, 0x6f); + /* BWD is not used in P-frame */ + vme_state_message[MODE_INTER_BWD] = 0; } else { - m_costf = lambda * 2.5; - m_cost = m_costf; - vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f); - m_costf = lambda * 5.5; - m_cost = m_costf; - vme_state_message[MODE_INTER_16X8] = intel_format_lutvalue(m_cost, 0x8f); - m_costf = lambda * 3.5; - m_cost = m_costf; - vme_state_message[MODE_INTER_8X8] = intel_format_lutvalue(m_cost, 0x6f); - m_costf = lambda * 5.0; - m_cost = m_costf; - vme_state_message[MODE_INTER_8X4] = intel_format_lutvalue(m_cost, 0x6f); - m_costf = lambda * 6.5; - m_cost = m_costf; - vme_state_message[MODE_INTER_4X4] = intel_format_lutvalue(m_cost, 0x6f); - m_costf = lambda * 1.5; - m_cost = m_costf; - vme_state_message[MODE_INTER_BWD] = intel_format_lutvalue(m_cost, 0x6f); + m_costf = lambda * 2.5; + m_cost = m_costf; + vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f); + m_costf = lambda * 5.5; + m_cost = m_costf; + vme_state_message[MODE_INTER_16X8] = intel_format_lutvalue(m_cost, 0x8f); + m_costf = lambda * 3.5; + m_cost = m_costf; + vme_state_message[MODE_INTER_8X8] = intel_format_lutvalue(m_cost, 0x6f); + m_costf = lambda * 5.0; + m_cost = m_costf; + vme_state_message[MODE_INTER_8X4] = intel_format_lutvalue(m_cost, 0x6f); + m_costf = lambda * 6.5; + m_cost = m_costf; + vme_state_message[MODE_INTER_4X4] = intel_format_lutvalue(m_cost, 0x6f); + m_costf = lambda * 1.5; + m_cost = m_costf; + vme_state_message[MODE_INTER_BWD] = intel_format_lutvalue(m_cost, 0x6f); } } } @@ -841,8 +841,8 @@ gen7_vme_scoreboard_init(VADriverContextP ctx, struct gen6_vme_context *vme_cont vme_context->gpe_context.vfe_desc5.scoreboard0.enable = 1; vme_context->gpe_context.vfe_desc5.scoreboard0.type = SCOREBOARD_STALLING; vme_context->gpe_context.vfe_desc5.scoreboard0.mask = (MB_SCOREBOARD_A | - MB_SCOREBOARD_B | - MB_SCOREBOARD_C); + MB_SCOREBOARD_B | + MB_SCOREBOARD_C); /* In VME prediction the current mb depends on the neighbour * A/B/C macroblock. So the left/up/up-right dependency should @@ -862,25 +862,25 @@ gen7_vme_scoreboard_init(VADriverContextP ctx, struct gen6_vme_context *vme_cont /* check whether the mb of (x_index, y_index) is out of bound */ static inline int loop_in_bounds(int x_index, int y_index, int first_mb, int num_mb, int mb_width, int mb_height) { - int mb_index; - if (x_index < 0 || x_index >= mb_width) - return -1; - if (y_index < 0 || y_index >= mb_height) - return -1; + int mb_index; + if (x_index < 0 || x_index >= mb_width) + return -1; + if (y_index < 0 || y_index >= mb_height) + return -1; - mb_index = y_index * mb_width + x_index; - if (mb_index < first_mb || mb_index > (first_mb + num_mb)) - return -1; - return 0; + mb_index = y_index * mb_width + x_index; + if (mb_index < first_mb || mb_index > (first_mb + num_mb)) + return -1; + return 0; } void gen7_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - int mb_width, int mb_height, - int kernel, - int transform_8x8_mode_flag, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + int mb_width, int mb_height, + int kernel, + int transform_8x8_mode_flag, + struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int mb_row; @@ -922,7 +922,7 @@ gen7_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx, if (x_inner != (mb_width -1)) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; score_dep |= MB_SCOREBOARD_C; - } + } } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); @@ -944,7 +944,7 @@ gen7_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx, xtemp_outer = mb_width - 2; if (xtemp_outer < 0) - xtemp_outer = 0; + xtemp_outer = 0; x_outer = xtemp_outer; y_outer = first_mb / mb_width; for (;!loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) { @@ -966,7 +966,7 @@ gen7_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx, if (x_inner != (mb_width -1)) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; score_dep |= MB_SCOREBOARD_C; - } + } } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); @@ -1001,198 +1001,198 @@ gen7_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx, static uint8_t intel_get_ref_idx_state_1(VAPictureH264 *va_pic, unsigned int frame_store_id) { - unsigned int is_long_term = - !!(va_pic->flags & VA_PICTURE_H264_LONG_TERM_REFERENCE); - unsigned int is_top_field = - !!(va_pic->flags & VA_PICTURE_H264_TOP_FIELD); - unsigned int is_bottom_field = - !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD); - - return ((is_long_term << 6) | - ((is_top_field ^ is_bottom_field ^ 1) << 5) | - (frame_store_id << 1) | - ((is_top_field ^ 1) & is_bottom_field)); + unsigned int is_long_term = + !!(va_pic->flags & VA_PICTURE_H264_LONG_TERM_REFERENCE); + unsigned int is_top_field = + !!(va_pic->flags & VA_PICTURE_H264_TOP_FIELD); + unsigned int is_bottom_field = + !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD); + + return ((is_long_term << 6) | + ((is_top_field ^ is_bottom_field ^ 1) << 5) | + (frame_store_id << 1) | + ((is_top_field ^ 1) & is_bottom_field)); } void intel_mfc_avc_ref_idx_state(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { - struct intel_batchbuffer *batch = encoder_context->base.batch; - struct i965_driver_data *i965 = i965_driver_data(ctx); - int slice_type; - struct object_surface *slice_obj_surface, *obj_surface; - int ref_surface_id; - unsigned int fref_entry, bref_entry; - int frame_index, i; - VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; - VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; - - fref_entry = 0x80808080; - bref_entry = 0x80808080; - slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); - - if (slice_type == SLICE_TYPE_P || slice_type == SLICE_TYPE_B) { - slice_obj_surface = NULL; - ref_surface_id = slice_param->RefPicList0[0].picture_id; - if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { - slice_obj_surface = SURFACE(ref_surface_id); - } - if (slice_obj_surface && slice_obj_surface->bo) { - obj_surface = slice_obj_surface; - } else { - obj_surface = encode_state->reference_objects[0]; - } - frame_index = -1; - for (i = 0; i < 16; i++) { - if (obj_surface == encode_state->reference_objects[i]) { - frame_index = i; - break; - } - } - if (frame_index == -1) { - WARN_ONCE("RefPicList0 is not found in DPB!\n"); - } else if (slice_obj_surface && slice_obj_surface->bo) { - /* This is passed by Slice_param->RefPicList0 */ - fref_entry &= ~(0xFF); - fref_entry += intel_get_ref_idx_state_1(&slice_param->RefPicList0[0], frame_index); - } else { - /* This is passed by the hacked mode */ - fref_entry &= ~(0xFF); - fref_entry += intel_get_ref_idx_state_1(&pic_param->ReferenceFrames[frame_index], frame_index); - } - } + struct intel_batchbuffer *batch = encoder_context->base.batch; + struct i965_driver_data *i965 = i965_driver_data(ctx); + int slice_type; + struct object_surface *slice_obj_surface, *obj_surface; + int ref_surface_id; + unsigned int fref_entry, bref_entry; + int frame_index, i; + VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; + VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; - if (slice_type == SLICE_TYPE_B) { - slice_obj_surface = NULL; - ref_surface_id = slice_param->RefPicList1[0].picture_id; - if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { - slice_obj_surface = SURFACE(ref_surface_id); - } - if (slice_obj_surface && slice_obj_surface->bo) { - obj_surface = slice_obj_surface; - } else { - obj_surface = encode_state->reference_objects[1]; - } - frame_index = -1; - for (i = 0; i < 16; i++) { - if (obj_surface == encode_state->reference_objects[i]) { - frame_index = i; - break; - } - } - if (frame_index == -1) { - WARN_ONCE("RefPicList1 is not found in DPB!\n"); - } else if (slice_obj_surface && slice_obj_surface->bo) { - bref_entry &= ~(0xFF); - bref_entry += intel_get_ref_idx_state_1(&slice_param->RefPicList1[0], frame_index); - } else { - bref_entry &= ~(0xFF); - bref_entry += intel_get_ref_idx_state_1(&pic_param->ReferenceFrames[frame_index], frame_index); - } + fref_entry = 0x80808080; + bref_entry = 0x80808080; + slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); + + if (slice_type == SLICE_TYPE_P || slice_type == SLICE_TYPE_B) { + slice_obj_surface = NULL; + ref_surface_id = slice_param->RefPicList0[0].picture_id; + if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { + slice_obj_surface = SURFACE(ref_surface_id); + } + if (slice_obj_surface && slice_obj_surface->bo) { + obj_surface = slice_obj_surface; + } else { + obj_surface = encode_state->reference_objects[0]; } + frame_index = -1; + for (i = 0; i < 16; i++) { + if (obj_surface == encode_state->reference_objects[i]) { + frame_index = i; + break; + } + } + if (frame_index == -1) { + WARN_ONCE("RefPicList0 is not found in DPB!\n"); + } else if (slice_obj_surface && slice_obj_surface->bo) { + /* This is passed by Slice_param->RefPicList0 */ + fref_entry &= ~(0xFF); + fref_entry += intel_get_ref_idx_state_1(&slice_param->RefPicList0[0], frame_index); + } else { + /* This is passed by the hacked mode */ + fref_entry &= ~(0xFF); + fref_entry += intel_get_ref_idx_state_1(&pic_param->ReferenceFrames[frame_index], frame_index); + } + } - BEGIN_BCS_BATCH(batch, 10); - OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8); - OUT_BCS_BATCH(batch, 0); //Select L0 - OUT_BCS_BATCH(batch, fref_entry); //Only 1 reference - for(i = 0; i < 7; i++) { - OUT_BCS_BATCH(batch, 0x80808080); - } - ADVANCE_BCS_BATCH(batch); - - BEGIN_BCS_BATCH(batch, 10); - OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8); - OUT_BCS_BATCH(batch, 1); //Select L1 - OUT_BCS_BATCH(batch, bref_entry); //Only 1 reference - for(i = 0; i < 7; i++) { - OUT_BCS_BATCH(batch, 0x80808080); - } - ADVANCE_BCS_BATCH(batch); + if (slice_type == SLICE_TYPE_B) { + slice_obj_surface = NULL; + ref_surface_id = slice_param->RefPicList1[0].picture_id; + if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { + slice_obj_surface = SURFACE(ref_surface_id); + } + if (slice_obj_surface && slice_obj_surface->bo) { + obj_surface = slice_obj_surface; + } else { + obj_surface = encode_state->reference_objects[1]; + } + frame_index = -1; + for (i = 0; i < 16; i++) { + if (obj_surface == encode_state->reference_objects[i]) { + frame_index = i; + break; + } + } + if (frame_index == -1) { + WARN_ONCE("RefPicList1 is not found in DPB!\n"); + } else if (slice_obj_surface && slice_obj_surface->bo) { + bref_entry &= ~(0xFF); + bref_entry += intel_get_ref_idx_state_1(&slice_param->RefPicList1[0], frame_index); + } else { + bref_entry &= ~(0xFF); + bref_entry += intel_get_ref_idx_state_1(&pic_param->ReferenceFrames[frame_index], frame_index); + } + } + + BEGIN_BCS_BATCH(batch, 10); + OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8); + OUT_BCS_BATCH(batch, 0); //Select L0 + OUT_BCS_BATCH(batch, fref_entry); //Only 1 reference + for(i = 0; i < 7; i++) { + OUT_BCS_BATCH(batch, 0x80808080); + } + ADVANCE_BCS_BATCH(batch); + + BEGIN_BCS_BATCH(batch, 10); + OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8); + OUT_BCS_BATCH(batch, 1); //Select L1 + OUT_BCS_BATCH(batch, bref_entry); //Only 1 reference + for(i = 0; i < 7; i++) { + OUT_BCS_BATCH(batch, 0x80808080); + } + ADVANCE_BCS_BATCH(batch); } void intel_vme_mpeg2_state_setup(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { - struct gen6_vme_context *vme_context = encoder_context->vme_context; - uint32_t *vme_state_message = (uint32_t *)(vme_context->vme_state_message); - VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; - int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; - int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; - uint32_t mv_x, mv_y; - VAEncSliceParameterBufferMPEG2 *slice_param = NULL; - VAEncPictureParameterBufferMPEG2 *pic_param = NULL; - slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer; - - if (vme_context->mpeg2_level == MPEG2_LEVEL_LOW) { - mv_x = 512; - mv_y = 64; - } else if (vme_context->mpeg2_level == MPEG2_LEVEL_MAIN) { - mv_x = 1024; - mv_y = 128; - } else if (vme_context->mpeg2_level == MPEG2_LEVEL_HIGH) { - mv_x = 2048; - mv_y = 128; - } else { - WARN_ONCE("Incorrect Mpeg2 level setting!\n"); - mv_x = 512; - mv_y = 64; - } + struct gen6_vme_context *vme_context = encoder_context->vme_context; + uint32_t *vme_state_message = (uint32_t *)(vme_context->vme_state_message); + VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; + int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; + int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; + uint32_t mv_x, mv_y; + VAEncSliceParameterBufferMPEG2 *slice_param = NULL; + VAEncPictureParameterBufferMPEG2 *pic_param = NULL; + slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer; + + if (vme_context->mpeg2_level == MPEG2_LEVEL_LOW) { + mv_x = 512; + mv_y = 64; + } else if (vme_context->mpeg2_level == MPEG2_LEVEL_MAIN) { + mv_x = 1024; + mv_y = 128; + } else if (vme_context->mpeg2_level == MPEG2_LEVEL_HIGH) { + mv_x = 2048; + mv_y = 128; + } else { + WARN_ONCE("Incorrect Mpeg2 level setting!\n"); + mv_x = 512; + mv_y = 64; + } - pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; - if (pic_param->picture_type != VAEncPictureTypeIntra) { - int qp, m_cost, j, mv_count; - float lambda, m_costf; - slice_param = (VAEncSliceParameterBufferMPEG2 *) - encode_state->slice_params_ext[0]->buffer; - qp = slice_param->quantiser_scale_code; - lambda = intel_lambda_qp(qp); - /* No Intra prediction. So it is zero */ - vme_state_message[MODE_INTRA_8X8] = 0; - vme_state_message[MODE_INTRA_4X4] = 0; - vme_state_message[MODE_INTER_MV0] = 0; - for (j = 1; j < 3; j++) { - m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; - m_cost = (int)m_costf; - vme_state_message[MODE_INTER_MV0 + j] = intel_format_lutvalue(m_cost, 0x6f); - } - mv_count = 3; - for (j = 4; j <= 64; j *= 2) { - m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; - m_cost = (int)m_costf; - vme_state_message[MODE_INTER_MV0 + mv_count] = - intel_format_lutvalue(m_cost, 0x6f); - mv_count++; - } - m_cost = lambda; - /* It can only perform the 16x16 search. So mode cost can be ignored for - * the other mode. for example: 16x8/8x8 - */ - vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost, 0x8f); - vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f); + pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; + if (pic_param->picture_type != VAEncPictureTypeIntra) { + int qp, m_cost, j, mv_count; + float lambda, m_costf; + slice_param = (VAEncSliceParameterBufferMPEG2 *) + encode_state->slice_params_ext[0]->buffer; + qp = slice_param->quantiser_scale_code; + lambda = intel_lambda_qp(qp); + /* No Intra prediction. So it is zero */ + vme_state_message[MODE_INTRA_8X8] = 0; + vme_state_message[MODE_INTRA_4X4] = 0; + vme_state_message[MODE_INTER_MV0] = 0; + for (j = 1; j < 3; j++) { + m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; + m_cost = (int)m_costf; + vme_state_message[MODE_INTER_MV0 + j] = intel_format_lutvalue(m_cost, 0x6f); + } + mv_count = 3; + for (j = 4; j <= 64; j *= 2) { + m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; + m_cost = (int)m_costf; + vme_state_message[MODE_INTER_MV0 + mv_count] = + intel_format_lutvalue(m_cost, 0x6f); + mv_count++; + } + m_cost = lambda; + /* It can only perform the 16x16 search. So mode cost can be ignored for + * the other mode. for example: 16x8/8x8 + */ + vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost, 0x8f); + vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f); - vme_state_message[MODE_INTER_16X8] = 0; - vme_state_message[MODE_INTER_8X8] = 0; - vme_state_message[MODE_INTER_8X4] = 0; - vme_state_message[MODE_INTER_4X4] = 0; - vme_state_message[MODE_INTER_BWD] = intel_format_lutvalue(m_cost, 0x6f); + vme_state_message[MODE_INTER_16X8] = 0; + vme_state_message[MODE_INTER_8X8] = 0; + vme_state_message[MODE_INTER_8X4] = 0; + vme_state_message[MODE_INTER_4X4] = 0; + vme_state_message[MODE_INTER_BWD] = intel_format_lutvalue(m_cost, 0x6f); - } - vme_state_message[MPEG2_MV_RANGE] = (mv_y << 16) | (mv_x); + } + vme_state_message[MPEG2_MV_RANGE] = (mv_y << 16) | (mv_x); - vme_state_message[MPEG2_PIC_WIDTH_HEIGHT] = (height_in_mbs << 16) | - width_in_mbs; + vme_state_message[MPEG2_PIC_WIDTH_HEIGHT] = (height_in_mbs << 16) | + width_in_mbs; } void gen7_vme_mpeg2_walker_fill_vme_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - int mb_width, int mb_height, - int kernel, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + int mb_width, int mb_height, + int kernel, + struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned int *command_ptr; @@ -1255,7 +1255,7 @@ gen7_vme_mpeg2_walker_fill_vme_batchbuffer(VADriverContextP ctx, xtemp_outer = mb_width - 2; if (xtemp_outer < 0) - xtemp_outer = 0; + xtemp_outer = 0; x_outer = xtemp_outer; y_outer = 0; for (;!loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) { diff --git a/src/gen6_vme.c b/src/gen6_vme.c index 443dda89..1d475179 100644 --- a/src/gen6_vme.c +++ b/src/gen6_vme.c @@ -221,36 +221,36 @@ gen6_vme_surface_setup(VADriverContextP ctx, slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); if (slice_type == SLICE_TYPE_P || slice_type == SLICE_TYPE_B) { - slice_obj_surface = NULL; - ref_surface_id = slice_param->RefPicList0[0].picture_id; - if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { - slice_obj_surface = SURFACE(ref_surface_id); - } - if (slice_obj_surface && slice_obj_surface->bo) { - obj_surface = slice_obj_surface; - } else { - obj_surface = encode_state->reference_objects[0]; - } - /* reference 0 */ - if (obj_surface && obj_surface->bo) - gen6_vme_source_surface_state(ctx, 1, obj_surface, encoder_context); + slice_obj_surface = NULL; + ref_surface_id = slice_param->RefPicList0[0].picture_id; + if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { + slice_obj_surface = SURFACE(ref_surface_id); + } + if (slice_obj_surface && slice_obj_surface->bo) { + obj_surface = slice_obj_surface; + } else { + obj_surface = encode_state->reference_objects[0]; + } + /* reference 0 */ + if (obj_surface && obj_surface->bo) + gen6_vme_source_surface_state(ctx, 1, obj_surface, encoder_context); } if (slice_type == SLICE_TYPE_B) { - /* reference 1 */ - slice_obj_surface = NULL; - ref_surface_id = slice_param->RefPicList1[0].picture_id; - if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { - slice_obj_surface = SURFACE(ref_surface_id); - } - if (slice_obj_surface && slice_obj_surface->bo) { - obj_surface = slice_obj_surface; - } else { - obj_surface = encode_state->reference_objects[0]; - } - - obj_surface = encode_state->reference_objects[1]; - if (obj_surface && obj_surface->bo) - gen6_vme_source_surface_state(ctx, 2, obj_surface, encoder_context); + /* reference 1 */ + slice_obj_surface = NULL; + ref_surface_id = slice_param->RefPicList1[0].picture_id; + if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { + slice_obj_surface = SURFACE(ref_surface_id); + } + if (slice_obj_surface && slice_obj_surface->bo) { + obj_surface = slice_obj_surface; + } else { + obj_surface = encode_state->reference_objects[0]; + } + + obj_surface = encode_state->reference_objects[1]; + if (obj_surface && obj_surface->bo) + gen6_vme_source_surface_state(ctx, 2, obj_surface, encoder_context); } } @@ -319,7 +319,7 @@ static VAStatus gen6_vme_constant_setup(VADriverContextP ctx, if (vme_context->h264_level >= 30) { mv_num = 16; if (vme_context->h264_level >= 31) - mv_num = 8; + mv_num = 8; } dri_bo_map(vme_context->gpe_context.curbe.bo, 1); @@ -579,7 +579,7 @@ static VAStatus gen6_vme_prepare(VADriverContextP ctx, struct gen6_vme_context *vme_context = encoder_context->vme_context; if (!vme_context->h264_level || - (vme_context->h264_level != pSequenceParameter->level_idc)) { + (vme_context->h264_level != pSequenceParameter->level_idc)) { vme_context->h264_level = pSequenceParameter->level_idc; } /*Setup all the memory object*/ @@ -657,7 +657,7 @@ Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *e vme_context = calloc(1, sizeof(struct gen6_vme_context)); vme_context->gpe_context.surface_state_binding_table.length = - (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; + (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6; vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data); diff --git a/src/gen6_vme.h b/src/gen6_vme.h index b130b58f..09d9673b 100644 --- a/src/gen6_vme.h +++ b/src/gen6_vme.h @@ -62,25 +62,25 @@ struct gen6_vme_context void (*vme_surface2_setup)(VADriverContextP ctx, - struct i965_gpe_context *gpe_context, - struct object_surface *obj_surface, - unsigned long binding_table_offset, - unsigned long surface_state_offset); + struct i965_gpe_context *gpe_context, + struct object_surface *obj_surface, + unsigned long binding_table_offset, + unsigned long surface_state_offset); void (*vme_media_rw_surface_setup)(VADriverContextP ctx, - struct i965_gpe_context *gpe_context, - struct object_surface *obj_surface, - unsigned long binding_table_offset, - unsigned long surface_state_offset); + struct i965_gpe_context *gpe_context, + struct object_surface *obj_surface, + unsigned long binding_table_offset, + unsigned long surface_state_offset); void (*vme_buffer_suface_setup)(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_buffer_surface *buffer_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void (*vme_media_chroma_surface_setup)(VADriverContextP ctx, - struct i965_gpe_context *gpe_context, - struct object_surface *obj_surface, - unsigned long binding_table_offset, - unsigned long surface_state_offset); + struct i965_gpe_context *gpe_context, + struct object_surface *obj_surface, + unsigned long binding_table_offset, + unsigned long surface_state_offset); void *vme_state_message; unsigned int h264_level; unsigned int video_coding_type; @@ -137,25 +137,25 @@ Bool gen7_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *e extern void gen7_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - int mb_width, int mb_height, - int kernel, - int transform_8x8_mode_flag, - struct intel_encoder_context *encoder_context); + struct encode_state *encode_state, + int mb_width, int mb_height, + int kernel, + int transform_8x8_mode_flag, + struct intel_encoder_context *encoder_context); extern void gen7_vme_scoreboard_init(VADriverContextP ctx, struct gen6_vme_context *vme_context); extern void intel_vme_mpeg2_state_setup(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context); + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context); extern void gen7_vme_mpeg2_walker_fill_vme_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - int mb_width, int mb_height, - int kernel, - struct intel_encoder_context *encoder_context); + struct encode_state *encode_state, + int mb_width, int mb_height, + int kernel, + struct intel_encoder_context *encoder_context); #endif /* _GEN6_VME_H_ */ diff --git a/src/gen75_mfc.c b/src/gen75_mfc.c index b3b6f881..4eecc9c7 100644 --- a/src/gen75_mfc.c +++ b/src/gen75_mfc.c @@ -86,8 +86,8 @@ static struct i965_kernel gen75_mfc_kernels[] = { static void gen75_mfc_pipe_mode_select(VADriverContextP ctx, - int standard_select, - struct intel_encoder_context *encoder_context) + int standard_select, + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -152,7 +152,7 @@ gen75_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *enco static void gen75_mfc_ind_obj_base_addr_state_bplus(VADriverContextP ctx, - struct intel_encoder_context *encoder_context) + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -161,11 +161,11 @@ gen75_mfc_ind_obj_base_addr_state_bplus(VADriverContextP ctx, BEGIN_BCS_BATCH(batch, 26); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2)); - /* the DW1-3 is for the MFX indirect bistream offset */ + /* the DW1-3 is for the MFX indirect bistream offset */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); - /* the DW4-5 is the MFX upper bound */ + /* the DW4-5 is the MFX upper bound */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); @@ -176,14 +176,14 @@ gen75_mfc_ind_obj_base_addr_state_bplus(VADriverContextP ctx, OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); - /* the DW11-15 is for MFX IT-COFF. Not used on encoder */ + /* the DW11-15 is for MFX IT-COFF. Not used on encoder */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); - /* the DW16-20 is for MFX indirect DBLK. Not used on encoder */ + /* the DW16-20 is for MFX indirect DBLK. Not used on encoder */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); @@ -247,7 +247,7 @@ gen75_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_con static void gen75_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -291,22 +291,22 @@ gen75_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state, (1 << 2) | /* Frame MB only flag */ (0 << 1) | /* MBAFF mode is in active */ (0 << 0)); /* Field picture flag */ - /* DW5 Trellis quantization */ + /* DW5 Trellis quantization */ OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */ OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */ (0xBB8 << 16) | /* InterMbMaxSz */ (0xEE8) ); /* IntraMbMaxSz */ OUT_BCS_BATCH(batch, 0); /* Reserved */ - /* DW8. QP delta */ + /* DW8. QP delta */ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ - /* DW10. Bit setting for MB */ + /* DW10. Bit setting for MB */ OUT_BCS_BATCH(batch, 0x8C000000); OUT_BCS_BATCH(batch, 0x00010000); - /* DW12. */ + /* DW12. */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0x02010100); - /* DW14. For short format */ + /* DW14. For short format */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); @@ -315,10 +315,10 @@ gen75_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state, static void gen75_mfc_qm_state(VADriverContextP ctx, - int qm_type, - unsigned int *qm, - int qm_length, - struct intel_encoder_context *encoder_context) + int qm_type, + unsigned int *qm, + int qm_length, + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; unsigned int qm_buffer[16]; @@ -352,10 +352,10 @@ gen75_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encod static void gen75_mfc_fqm_state(VADriverContextP ctx, - int fqm_type, - unsigned int *fqm, - int fqm_length, - struct intel_encoder_context *encoder_context) + int fqm_type, + unsigned int *fqm, + int fqm_length, + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; unsigned int fqm_buffer[32]; @@ -393,9 +393,9 @@ gen75_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *enco static void gen75_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context, - unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw, - int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag, - struct intel_batchbuffer *batch) + unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw, + int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag, + struct intel_batchbuffer *batch) { if (batch == NULL) batch = encoder_context->base.batch; @@ -418,8 +418,8 @@ gen75_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context * static void gen75_mfc_init(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -519,7 +519,7 @@ static void gen75_mfc_init(VADriverContextP ctx, static void gen75_mfc_pipe_buf_addr_state_bplus(VADriverContextP ctx, - struct intel_encoder_context *encoder_context) + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -537,9 +537,9 @@ gen75_mfc_pipe_buf_addr_state_bplus(VADriverContextP ctx, else OUT_BCS_BATCH(batch, 0); /* pre output addr */ - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); - /* the DW4-6 is for the post_deblocking */ + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + /* the DW4-6 is for the post_deblocking */ if (mfc_context->post_deblocking_output.bo) OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo, @@ -547,37 +547,37 @@ gen75_mfc_pipe_buf_addr_state_bplus(VADriverContextP ctx, 0); /* post output addr */ else OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); - /* the DW7-9 is for the uncompressed_picture */ + /* the DW7-9 is for the uncompressed_picture */ OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* uncompressed data */ - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); - /* the DW10-12 is for the mb status */ + /* the DW10-12 is for the mb status */ OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* StreamOut data*/ - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); - /* the DW13-15 is for the intra_row_store_scratch */ + /* the DW13-15 is for the intra_row_store_scratch */ OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); - /* the DW16-18 is for the deblocking filter */ + /* the DW16-18 is for the deblocking filter */ OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); /* the DW 19-50 is for Reference pictures*/ for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) { @@ -590,25 +590,25 @@ gen75_mfc_pipe_buf_addr_state_bplus(VADriverContextP ctx, } OUT_BCS_BATCH(batch, 0); } - OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); - /* The DW 52-54 is for the MB status buffer */ + /* The DW 52-54 is for the MB status buffer */ OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* Macroblock status buffer*/ - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); - /* the DW 55-57 is the ILDB buffer */ - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); + /* the DW 55-57 is the ILDB buffer */ + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); - /* the DW 58-60 is the second ILDB buffer */ - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); + /* the DW 58-60 is the second ILDB buffer */ + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } @@ -669,14 +669,14 @@ gen75_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* Macroblock status buffer*/ - OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_avc_directmode_state_bplus(VADriverContextP ctx, - struct intel_encoder_context *encoder_context) + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -700,15 +700,15 @@ gen75_mfc_avc_directmode_state_bplus(VADriverContextP ctx, OUT_BCS_BATCH(batch, 0); } } - OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); - /* the DW34-36 is the MV for the current reference */ - OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo, - I915_GEM_DOMAIN_INSTRUCTION, 0, - 0); + /* the DW34-36 is the MV for the current reference */ + OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); /* POL list */ for(i = 0; i < 32; i++) { @@ -761,7 +761,7 @@ gen75_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_contex static void gen75_mfc_bsp_buf_base_addr_state_bplus(VADriverContextP ctx, - struct intel_encoder_context *encoder_context) + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -775,12 +775,12 @@ gen75_mfc_bsp_buf_base_addr_state_bplus(VADriverContextP ctx, OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); - /* the DW4-6 is for MPR Row Store Scratch Buffer Base Address */ + /* the DW4-6 is for MPR Row Store Scratch Buffer Base Address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); - /* the DW7-9 is for Bitplane Read Buffer Base Address */ + /* the DW7-9 is for Bitplane Read Buffer Base Address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); @@ -814,8 +814,8 @@ gen75_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_con static void gen75_mfc_avc_pipeline_picture_programing( VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -833,8 +833,8 @@ static void gen75_mfc_avc_pipeline_picture_programing( VADriverContextP ctx, static VAStatus gen75_mfc_run(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; @@ -846,9 +846,9 @@ static VAStatus gen75_mfc_run(VADriverContextP ctx, static VAStatus gen75_mfc_stop(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int *encoded_bits_size) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + int *encoded_bits_size) { VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; @@ -865,13 +865,13 @@ gen75_mfc_stop(VADriverContextP ctx, static void gen75_mfc_avc_slice_state(VADriverContextP ctx, - VAEncPictureParameterBufferH264 *pic_param, - VAEncSliceParameterBufferH264 *slice_param, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int rate_control_enable, - int qp, - struct intel_batchbuffer *batch) + VAEncPictureParameterBufferH264 *pic_param, + VAEncSliceParameterBufferH264 *slice_param, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + int rate_control_enable, + int qp, + struct intel_batchbuffer *batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; @@ -985,10 +985,10 @@ gen75_mfc_avc_slice_state(VADriverContextP ctx, static int gen75_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, - int qp,unsigned int *msg, - struct intel_encoder_context *encoder_context, - unsigned char target_mb_size, unsigned char max_mb_size, - struct intel_batchbuffer *batch) + int qp,unsigned int *msg, + struct intel_encoder_context *encoder_context, + unsigned char target_mb_size, unsigned char max_mb_size, + struct intel_batchbuffer *batch) { int len_in_dwords = 12; unsigned int intra_msg; @@ -1035,13 +1035,13 @@ gen75_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, static int gen75_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, - unsigned int *msg, unsigned int offset, - struct intel_encoder_context *encoder_context, - unsigned char target_mb_size,unsigned char max_mb_size, int slice_type, - struct intel_batchbuffer *batch) + unsigned int *msg, unsigned int offset, + struct intel_encoder_context *encoder_context, + unsigned char target_mb_size,unsigned char max_mb_size, int slice_type, + struct intel_batchbuffer *batch) { int len_in_dwords = 12; - unsigned int inter_msg = 0; + unsigned int inter_msg = 0; if (batch == NULL) batch = encoder_context->base.batch; { @@ -1053,30 +1053,30 @@ gen75_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, i * command. */ if ((msg[0] & INTER_MODE_MASK) == INTER_8X16) { - /* MV[0] and MV[2] are replicated */ - mv_ptr[4] = mv_ptr[0]; - mv_ptr[5] = mv_ptr[1]; - mv_ptr[2] = mv_ptr[8]; - mv_ptr[3] = mv_ptr[9]; - mv_ptr[6] = mv_ptr[8]; - mv_ptr[7] = mv_ptr[9]; + /* MV[0] and MV[2] are replicated */ + mv_ptr[4] = mv_ptr[0]; + mv_ptr[5] = mv_ptr[1]; + mv_ptr[2] = mv_ptr[8]; + mv_ptr[3] = mv_ptr[9]; + mv_ptr[6] = mv_ptr[8]; + mv_ptr[7] = mv_ptr[9]; } else if ((msg[0] & INTER_MODE_MASK) == INTER_16X8) { - /* MV[0] and MV[1] are replicated */ - mv_ptr[2] = mv_ptr[0]; - mv_ptr[3] = mv_ptr[1]; - mv_ptr[4] = mv_ptr[16]; - mv_ptr[5] = mv_ptr[17]; - mv_ptr[6] = mv_ptr[24]; - mv_ptr[7] = mv_ptr[25]; + /* MV[0] and MV[1] are replicated */ + mv_ptr[2] = mv_ptr[0]; + mv_ptr[3] = mv_ptr[1]; + mv_ptr[4] = mv_ptr[16]; + mv_ptr[5] = mv_ptr[17]; + mv_ptr[6] = mv_ptr[24]; + mv_ptr[7] = mv_ptr[25]; } else if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) && - !(msg[1] & SUBMB_SHAPE_MASK)) { - /* Don't touch MV[0] or MV[1] */ - mv_ptr[2] = mv_ptr[8]; - mv_ptr[3] = mv_ptr[9]; - mv_ptr[4] = mv_ptr[16]; - mv_ptr[5] = mv_ptr[17]; - mv_ptr[6] = mv_ptr[24]; - mv_ptr[7] = mv_ptr[25]; + !(msg[1] & SUBMB_SHAPE_MASK)) { + /* Don't touch MV[0] or MV[1] */ + mv_ptr[2] = mv_ptr[8]; + mv_ptr[3] = mv_ptr[9]; + mv_ptr[4] = mv_ptr[16]; + mv_ptr[5] = mv_ptr[17]; + mv_ptr[6] = mv_ptr[24]; + mv_ptr[7] = mv_ptr[25]; } } @@ -1084,21 +1084,21 @@ gen75_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, i OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); - inter_msg = 32; - /* MV quantity */ - if ((msg[0] & INTER_MODE_MASK) == INTER_8X8) { - if (msg[1] & SUBMB_SHAPE_MASK) - inter_msg = 128; - } + inter_msg = 32; + /* MV quantity */ + if ((msg[0] & INTER_MODE_MASK) == INTER_8X8) { + if (msg[1] & SUBMB_SHAPE_MASK) + inter_msg = 128; + } OUT_BCS_BATCH(batch, inter_msg); /* 32 MV*/ OUT_BCS_BATCH(batch, offset); - inter_msg = msg[0] & (0x1F00FFFF); - inter_msg |= INTER_MV8; - inter_msg |= ((1 << 19) | (1 << 18) | (1 << 17)); - if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) && - (msg[1] & SUBMB_SHAPE_MASK)) { - inter_msg |= INTER_MV32; - } + inter_msg = msg[0] & (0x1F00FFFF); + inter_msg |= INTER_MV8; + inter_msg |= ((1 << 19) | (1 << 18) | (1 << 17)); + if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) && + (msg[1] & SUBMB_SHAPE_MASK)) { + inter_msg |= INTER_MV32; + } OUT_BCS_BATCH(batch, inter_msg); @@ -1114,7 +1114,7 @@ gen75_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, i OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ #endif - inter_msg = msg[1] >> 8; + inter_msg = msg[1] >> 8; /*Stuff for Inter MB*/ OUT_BCS_BATCH(batch, inter_msg); OUT_BCS_BATCH(batch, 0x0); @@ -1139,10 +1139,10 @@ gen75_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, i static void gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int slice_index, - struct intel_batchbuffer *slice_batch) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + int slice_index, + struct intel_batchbuffer *slice_batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; @@ -1175,10 +1175,10 @@ gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, assert(qp >= 0 && qp < 52); gen75_mfc_avc_slice_state(ctx, - pPicParameter, - pSliceParameter, - encode_state, encoder_context, - (rate_control_mode == VA_RC_CBR), qp, slice_batch); + pPicParameter, + pSliceParameter, + encode_state, encoder_context, + (rate_control_mode == VA_RC_CBR), qp, slice_batch); if ( slice_index == 0) intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); @@ -1242,8 +1242,8 @@ gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, static dri_bo * gen75_mfc_avc_software_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch; @@ -1278,8 +1278,8 @@ gen75_mfc_avc_software_batchbuffer(VADriverContextP ctx, static void gen75_mfc_batchbuffer_surfaces_input(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; @@ -1301,8 +1301,8 @@ gen75_mfc_batchbuffer_surfaces_input(VADriverContextP ctx, static void gen75_mfc_batchbuffer_surfaces_output(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); @@ -1326,8 +1326,8 @@ gen75_mfc_batchbuffer_surfaces_output(VADriverContextP ctx, static void gen75_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { gen75_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context); gen75_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context); @@ -1335,8 +1335,8 @@ gen75_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx, static void gen75_mfc_batchbuffer_idrt_setup(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_interface_descriptor_data *desc; @@ -1378,8 +1378,8 @@ gen75_mfc_batchbuffer_idrt_setup(VADriverContextP ctx, static void gen75_mfc_batchbuffer_constant_setup(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -1388,19 +1388,19 @@ gen75_mfc_batchbuffer_constant_setup(VADriverContextP ctx, static void gen75_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch, - int index, - int head_offset, - int batchbuffer_offset, - int head_size, - int tail_size, - int number_mb_cmds, - int first_object, - int last_object, - int last_slice, - int mb_x, - int mb_y, - int width_in_mbs, - int qp) + int index, + int head_offset, + int batchbuffer_offset, + int head_size, + int tail_size, + int number_mb_cmds, + int first_object, + int last_object, + int last_slice, + int mb_x, + int mb_y, + int width_in_mbs, + int qp) { BEGIN_BATCH(batch, 12); @@ -1434,14 +1434,14 @@ gen75_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch, static void gen75_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx, - struct intel_encoder_context *encoder_context, - VAEncSliceParameterBufferH264 *slice_param, - int head_offset, - unsigned short head_size, - unsigned short tail_size, - int batchbuffer_offset, - int qp, - int last_slice) + struct intel_encoder_context *encoder_context, + VAEncSliceParameterBufferH264 *slice_param, + int head_offset, + unsigned short head_size, + unsigned short tail_size, + int batchbuffer_offset, + int qp, + int last_slice) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -1464,19 +1464,19 @@ gen75_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx, starting_mb += number_mb_cmds; gen75_mfc_batchbuffer_emit_object_command(batch, - index, - head_offset, - batchbuffer_offset, - head_size, - tail_size, - number_mb_cmds, - first_object, - last_object, - last_slice, - mb_x, - mb_y, - width_in_mbs, - qp); + index, + head_offset, + batchbuffer_offset, + head_size, + tail_size, + number_mb_cmds, + first_object, + last_object, + last_slice, + mb_x, + mb_y, + width_in_mbs, + qp); if (first_object) { head_offset += head_size; @@ -1502,19 +1502,19 @@ gen75_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx, starting_mb += number_mb_cmds; gen75_mfc_batchbuffer_emit_object_command(batch, - index, - head_offset, - batchbuffer_offset, - head_size, - tail_size, - number_mb_cmds, - first_object, - last_object, - last_slice, - mb_x, - mb_y, - width_in_mbs, - qp); + index, + head_offset, + batchbuffer_offset, + head_size, + tail_size, + number_mb_cmds, + first_object, + last_object, + last_slice, + mb_x, + mb_y, + width_in_mbs, + qp); } } @@ -1523,10 +1523,10 @@ gen75_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx, */ static int gen75_mfc_avc_batchbuffer_slice(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int slice_index, - int batchbuffer_offset) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + int slice_index, + int batchbuffer_offset) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer; @@ -1559,13 +1559,13 @@ gen75_mfc_avc_batchbuffer_slice(VADriverContextP ctx, head_offset = old_used / 16; gen75_mfc_avc_slice_state(ctx, - pPicParameter, - pSliceParameter, - encode_state, - encoder_context, - (rate_control_mode == VA_RC_CBR), - qp, - slice_batch); + pPicParameter, + pSliceParameter, + encode_state, + encoder_context, + (rate_control_mode == VA_RC_CBR), + qp, + slice_batch); if (slice_index == 0) intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); @@ -1621,22 +1621,22 @@ gen75_mfc_avc_batchbuffer_slice(VADriverContextP ctx, gen75_mfc_avc_batchbuffer_slice_command(ctx, - encoder_context, - pSliceParameter, - head_offset, - head_size, - tail_size, - batchbuffer_offset, - qp, - last_slice); + encoder_context, + pSliceParameter, + head_offset, + head_size, + tail_size, + batchbuffer_offset, + qp, + last_slice); return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD; } static void gen75_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct intel_batchbuffer *batch = encoder_context->base.batch; @@ -1655,8 +1655,8 @@ gen75_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx, static void gen75_mfc_build_avc_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { gen75_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context); gen75_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context); @@ -1666,8 +1666,8 @@ gen75_mfc_build_avc_batchbuffer(VADriverContextP ctx, static dri_bo * gen75_mfc_avc_hardware_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -1681,8 +1681,8 @@ gen75_mfc_avc_hardware_batchbuffer(VADriverContextP ctx, static void gen75_mfc_avc_pipeline_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; dri_bo *slice_batch_bo; @@ -1723,8 +1723,8 @@ gen75_mfc_avc_pipeline_programing(VADriverContextP ctx, static VAStatus gen75_mfc_avc_encode_picture(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; unsigned int rate_control_mode = encoder_context->rate_control_mode; @@ -1832,7 +1832,7 @@ static void gen75_mfc_mpeg2_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned char intra_qm[64] = { - 8, 16, 19, 22, 26, 27, 29, 34, + 8, 16, 19, 22, 26, 27, 29, 34, 16, 16, 22, 24, 27, 29, 34, 37, 19, 22, 26, 27, 29, 34, 34, 38, 22, 22, 26, 27, 29, 34, 37, 40, @@ -1861,14 +1861,14 @@ static void gen75_mfc_mpeg2_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned short intra_fqm[64] = { - 65536/0x8, 65536/0x10, 65536/0x13, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, - 65536/0x10, 65536/0x10, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1b, 65536/0x1b, 65536/0x1d, - 65536/0x13, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, 65536/0x1d, 65536/0x1d, 65536/0x23, - 65536/0x16, 65536/0x18, 65536/0x1b, 65536/0x1b, 65536/0x13, 65536/0x20, 65536/0x22, 65536/0x26, - 65536/0x1a, 65536/0x1b, 65536/0x13, 65536/0x13, 65536/0x20, 65536/0x23, 65536/0x26, 65536/0x2e, - 65536/0x1b, 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x23, 65536/0x28, 65536/0x2e, 65536/0x38, - 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x25, 65536/0x28, 65536/0x30, 65536/0x38, 65536/0x45, - 65536/0x22, 65536/0x25, 65536/0x26, 65536/0x28, 65536/0x30, 65536/0x3a, 65536/0x45, 65536/0x53, + 65536/0x8, 65536/0x10, 65536/0x13, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, + 65536/0x10, 65536/0x10, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1b, 65536/0x1b, 65536/0x1d, + 65536/0x13, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, 65536/0x1d, 65536/0x1d, 65536/0x23, + 65536/0x16, 65536/0x18, 65536/0x1b, 65536/0x1b, 65536/0x13, 65536/0x20, 65536/0x22, 65536/0x26, + 65536/0x1a, 65536/0x1b, 65536/0x13, 65536/0x13, 65536/0x20, 65536/0x23, 65536/0x26, 65536/0x2e, + 65536/0x1b, 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x23, 65536/0x28, 65536/0x2e, 65536/0x38, + 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x25, 65536/0x28, 65536/0x30, 65536/0x38, 65536/0x45, + 65536/0x22, 65536/0x25, 65536/0x26, 65536/0x28, 65536/0x30, 65536/0x3a, 65536/0x45, 65536/0x53, }; unsigned short non_intra_fqm[64] = { @@ -2251,34 +2251,34 @@ gen75_mfc_mpeg2_pipeline_slice_group(VADriverContextP ctx, intra_rdo = msg[AVC_INTRA_RDO_OFFSET] & AVC_RDO_MASK; if (intra_rdo < inter_rdo) - gen75_mfc_mpeg2_pak_object_intra(ctx, - encoder_context, - h_pos, v_pos, - first_mb_in_slice, - last_mb_in_slice, - first_mb_in_slice_group, - last_mb_in_slice_group, - 0x1a, - slice_param->quantiser_scale_code, - 0x3f, - 0, - 0xff, - slice_batch); + gen75_mfc_mpeg2_pak_object_intra(ctx, + encoder_context, + h_pos, v_pos, + first_mb_in_slice, + last_mb_in_slice, + first_mb_in_slice_group, + last_mb_in_slice_group, + 0x1a, + slice_param->quantiser_scale_code, + 0x3f, + 0, + 0xff, + slice_batch); else - gen75_mfc_mpeg2_pak_object_inter(ctx, - encode_state, - encoder_context, - msg, - width_in_mbs, height_in_mbs, - h_pos, v_pos, - first_mb_in_slice, - last_mb_in_slice, - first_mb_in_slice_group, - last_mb_in_slice_group, - slice_param->quantiser_scale_code, - 0, - 0xff, - slice_batch); + gen75_mfc_mpeg2_pak_object_inter(ctx, + encode_state, + encoder_context, + msg, + width_in_mbs, height_in_mbs, + h_pos, v_pos, + first_mb_in_slice, + last_mb_in_slice, + first_mb_in_slice_group, + last_mb_in_slice_group, + slice_param->quantiser_scale_code, + 0, + 0xff, + slice_batch); } } @@ -2553,9 +2553,9 @@ gen75_mfc_context_destroy(void *context) } static VAStatus gen75_mfc_pipeline(VADriverContextP ctx, - VAProfile profile, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + VAProfile profile, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { VAStatus vaStatus; diff --git a/src/gen75_vme.c b/src/gen75_vme.c index 3e769ed0..515d8c00 100644 --- a/src/gen75_vme.c +++ b/src/gen75_vme.c @@ -282,36 +282,36 @@ gen75_vme_surface_setup(VADriverContextP ctx, slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); if (slice_type == SLICE_TYPE_P || slice_type == SLICE_TYPE_B) { - slice_obj_surface = NULL; - ref_surface_id = slice_param->RefPicList0[0].picture_id; - if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { - slice_obj_surface = SURFACE(ref_surface_id); - } - if (slice_obj_surface && slice_obj_surface->bo) { - obj_surface = slice_obj_surface; - } else { - obj_surface = encode_state->reference_objects[0]; - } - /* reference 0 */ - if (obj_surface && obj_surface->bo) - gen75_vme_source_surface_state(ctx, 1, obj_surface, encoder_context); + slice_obj_surface = NULL; + ref_surface_id = slice_param->RefPicList0[0].picture_id; + if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { + slice_obj_surface = SURFACE(ref_surface_id); + } + if (slice_obj_surface && slice_obj_surface->bo) { + obj_surface = slice_obj_surface; + } else { + obj_surface = encode_state->reference_objects[0]; + } + /* reference 0 */ + if (obj_surface && obj_surface->bo) + gen75_vme_source_surface_state(ctx, 1, obj_surface, encoder_context); } if (slice_type == SLICE_TYPE_B) { - /* reference 1 */ - slice_obj_surface = NULL; - ref_surface_id = slice_param->RefPicList1[0].picture_id; - if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { - slice_obj_surface = SURFACE(ref_surface_id); - } - if (slice_obj_surface && slice_obj_surface->bo) { - obj_surface = slice_obj_surface; - } else { - obj_surface = encode_state->reference_objects[0]; - } + /* reference 1 */ + slice_obj_surface = NULL; + ref_surface_id = slice_param->RefPicList1[0].picture_id; + if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { + slice_obj_surface = SURFACE(ref_surface_id); + } + if (slice_obj_surface && slice_obj_surface->bo) { + obj_surface = slice_obj_surface; + } else { + obj_surface = encode_state->reference_objects[0]; + } - obj_surface = encode_state->reference_objects[1]; - if (obj_surface && obj_surface->bo) - gen75_vme_source_surface_state(ctx, 2, obj_surface, encoder_context); + obj_surface = encode_state->reference_objects[1]; + if (obj_surface && obj_surface->bo) + gen75_vme_source_surface_state(ctx, 2, obj_surface, encoder_context); } } @@ -618,35 +618,35 @@ static void gen75_vme_pipeline_programing(VADriverContextP ctx, for (s = 0; s < encode_state->num_slice_params_ext; s++) { pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer; if ((pSliceParameter->macroblock_address % width_in_mbs)) { - allow_hwscore = false; - break; + allow_hwscore = false; + break; } } if ((pSliceParameter->slice_type == SLICE_TYPE_I) || (pSliceParameter->slice_type == SLICE_TYPE_I)) { kernel_shader = VME_INTRA_SHADER; - } else if ((pSliceParameter->slice_type == SLICE_TYPE_P) || - (pSliceParameter->slice_type == SLICE_TYPE_SP)) { + } else if ((pSliceParameter->slice_type == SLICE_TYPE_P) || + (pSliceParameter->slice_type == SLICE_TYPE_SP)) { kernel_shader = VME_INTER_SHADER; - } else { + } else { kernel_shader = VME_BINTER_SHADER; if (!allow_hwscore) - kernel_shader = VME_INTER_SHADER; - } + kernel_shader = VME_INTER_SHADER; + } if (allow_hwscore) gen7_vme_walker_fill_vme_batchbuffer(ctx, - encode_state, - width_in_mbs, height_in_mbs, - kernel_shader, - pPicParameter->pic_fields.bits.transform_8x8_mode_flag, - encoder_context); + encode_state, + width_in_mbs, height_in_mbs, + kernel_shader, + pPicParameter->pic_fields.bits.transform_8x8_mode_flag, + encoder_context); else gen75_vme_fill_vme_batchbuffer(ctx, - encode_state, - width_in_mbs, height_in_mbs, - kernel_shader, - pPicParameter->pic_fields.bits.transform_8x8_mode_flag, - encoder_context); + encode_state, + width_in_mbs, height_in_mbs, + kernel_shader, + pPicParameter->pic_fields.bits.transform_8x8_mode_flag, + encoder_context); intel_batchbuffer_start_atomic(batch, 0x1000); gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch); @@ -948,17 +948,17 @@ gen75_vme_mpeg2_pipeline_programing(VADriverContextP ctx, if (allow_hwscore) gen7_vme_mpeg2_walker_fill_vme_batchbuffer(ctx, - encode_state, - width_in_mbs, height_in_mbs, - kernel_shader, - encoder_context); + encode_state, + width_in_mbs, height_in_mbs, + kernel_shader, + encoder_context); else gen75_vme_mpeg2_fill_vme_batchbuffer(ctx, - encode_state, - width_in_mbs, height_in_mbs, - kernel_shader, - 0, - encoder_context); + encode_state, + width_in_mbs, height_in_mbs, + kernel_shader, + 0, + encoder_context); intel_batchbuffer_start_atomic(batch, 0x1000); gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch); @@ -985,7 +985,7 @@ gen75_vme_mpeg2_prepare(VADriverContextP ctx, struct gen6_vme_context *vme_context = encoder_context->vme_context; if ((!vme_context->mpeg2_level) || - (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) { + (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) { vme_context->mpeg2_level = seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK; } @@ -1044,7 +1044,7 @@ Bool gen75_vme_context_init(VADriverContextP ctx, struct intel_encoder_context * { struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context)); struct i965_kernel *vme_kernel_list = NULL; - int i965_kernel_num; + int i965_kernel_num; switch (encoder_context->codec) { case CODEC_H264: diff --git a/src/gen7_mfc.c b/src/gen7_mfc.c index e35ca85e..1412a149 100644 --- a/src/gen7_mfc.c +++ b/src/gen7_mfc.c @@ -46,7 +46,7 @@ gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context); extern void gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, - struct intel_encoder_context *encoder_context); + struct intel_encoder_context *encoder_context); extern void gen6_mfc_init(VADriverContextP ctx, struct encode_state *encode_state, @@ -208,13 +208,13 @@ gen7_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state, BEGIN_BCS_BATCH(batch, 16); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2)); - /*DW1 frame size */ + /*DW1 frame size */ OUT_BCS_BATCH(batch, ((width_in_mbs * height_in_mbs) & 0xFFFF)); OUT_BCS_BATCH(batch, ((height_in_mbs - 1) << 16) | ((width_in_mbs - 1) << 0)); - /*DW3 Qp setting */ + /*DW3 Qp setting */ OUT_BCS_BATCH(batch, (0 << 24) | /* Second Chroma QP Offset */ (0 << 16) | /* Chroma QP Offset */ @@ -240,20 +240,20 @@ gen7_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state, (1 << 2) | /* Frame MB only flag */ (0 << 1) | /* MBAFF mode is in active */ (0 << 0)); /* Field picture flag */ - /*DW5 trequllis quantization */ + /*DW5 trequllis quantization */ OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */ OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */ (0xBB8 << 16) | /* InterMbMaxSz */ (0xEE8) ); /* IntraMbMaxSz */ - /* DW7 */ + /* DW7 */ OUT_BCS_BATCH(batch, 0); /* Reserved */ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ - /* DW10 frame bit setting */ + /* DW10 frame bit setting */ OUT_BCS_BATCH(batch, 0x8C000000); OUT_BCS_BATCH(batch, 0x00010000); OUT_BCS_BATCH(batch, 0); - /* DW13 Ref setting */ + /* DW13 Ref setting */ OUT_BCS_BATCH(batch, 0x02010100); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); @@ -373,8 +373,8 @@ va_to_gen7_mpeg2_picture_type[3] = { static void gen7_mfc_mpeg2_pic_state(VADriverContextP ctx, - struct intel_encoder_context *encoder_context, - struct encode_state *encode_state) + struct intel_encoder_context *encoder_context, + struct encode_state *encode_state) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -434,7 +434,7 @@ static void gen7_mfc_mpeg2_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned char intra_qm[64] = { - 8, 16, 19, 22, 26, 27, 29, 34, + 8, 16, 19, 22, 26, 27, 29, 34, 16, 16, 22, 24, 27, 29, 34, 37, 19, 22, 26, 27, 29, 34, 34, 38, 22, 22, 26, 27, 29, 34, 37, 40, @@ -463,14 +463,14 @@ static void gen7_mfc_mpeg2_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned short intra_fqm[64] = { - 65536/0x8, 65536/0x10, 65536/0x13, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, - 65536/0x10, 65536/0x10, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1b, 65536/0x1b, 65536/0x1d, - 65536/0x13, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, 65536/0x1d, 65536/0x1d, 65536/0x23, - 65536/0x16, 65536/0x18, 65536/0x1b, 65536/0x1b, 65536/0x13, 65536/0x20, 65536/0x22, 65536/0x26, - 65536/0x1a, 65536/0x1b, 65536/0x13, 65536/0x13, 65536/0x20, 65536/0x23, 65536/0x26, 65536/0x2e, - 65536/0x1b, 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x23, 65536/0x28, 65536/0x2e, 65536/0x38, - 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x25, 65536/0x28, 65536/0x30, 65536/0x38, 65536/0x45, - 65536/0x22, 65536/0x25, 65536/0x26, 65536/0x28, 65536/0x30, 65536/0x3a, 65536/0x45, 65536/0x53, + 65536/0x8, 65536/0x10, 65536/0x13, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, + 65536/0x10, 65536/0x10, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1b, 65536/0x1b, 65536/0x1d, + 65536/0x13, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, 65536/0x1d, 65536/0x1d, 65536/0x23, + 65536/0x16, 65536/0x18, 65536/0x1b, 65536/0x1b, 65536/0x13, 65536/0x20, 65536/0x22, 65536/0x26, + 65536/0x1a, 65536/0x1b, 65536/0x13, 65536/0x13, 65536/0x20, 65536/0x23, 65536/0x26, 65536/0x2e, + 65536/0x1b, 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x23, 65536/0x28, 65536/0x2e, 65536/0x38, + 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x25, 65536/0x28, 65536/0x30, 65536/0x38, 65536/0x45, + 65536/0x22, 65536/0x25, 65536/0x26, 65536/0x28, 65536/0x30, 65536/0x3a, 65536/0x45, 65536/0x53, }; unsigned short non_intra_fqm[64] = { @@ -490,14 +490,14 @@ gen7_mfc_mpeg2_fqm_state(VADriverContextP ctx, struct intel_encoder_context *enc static void gen7_mfc_mpeg2_slicegroup_state(VADriverContextP ctx, - struct intel_encoder_context *encoder_context, - int x, int y, - int next_x, int next_y, - int is_fisrt_slice_group, - int is_last_slice_group, - int intra_slice, - int qp, - struct intel_batchbuffer *batch) + struct intel_encoder_context *encoder_context, + int x, int y, + int next_x, int next_y, + int is_fisrt_slice_group, + int is_last_slice_group, + int intra_slice, + int qp, + struct intel_batchbuffer *batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -537,18 +537,18 @@ gen7_mfc_mpeg2_slicegroup_state(VADriverContextP ctx, static int gen7_mfc_mpeg2_pak_object_intra(VADriverContextP ctx, - struct intel_encoder_context *encoder_context, - int x, int y, - int first_mb_in_slice, - int last_mb_in_slice, - int first_mb_in_slice_group, - int last_mb_in_slice_group, - int mb_type, - int qp_scale_code, - int coded_block_pattern, - unsigned char target_size_in_word, - unsigned char max_size_in_word, - struct intel_batchbuffer *batch) + struct intel_encoder_context *encoder_context, + int x, int y, + int first_mb_in_slice, + int last_mb_in_slice, + int first_mb_in_slice_group, + int last_mb_in_slice_group, + int mb_type, + int qp_scale_code, + int coded_block_pattern, + unsigned char target_size_in_word, + unsigned char max_size_in_word, + struct intel_batchbuffer *batch) { int len_in_dwords = 9; @@ -634,19 +634,19 @@ mpeg2_motion_vector(int mv, int pos, int display_max, int f_code) static int gen7_mfc_mpeg2_pak_object_inter(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - unsigned int *msg, - int width_in_mbs, int height_in_mbs, - int x, int y, - int first_mb_in_slice, - int last_mb_in_slice, - int first_mb_in_slice_group, - int last_mb_in_slice_group, - int qp_scale_code, - unsigned char target_size_in_word, - unsigned char max_size_in_word, - struct intel_batchbuffer *batch) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + unsigned int *msg, + int width_in_mbs, int height_in_mbs, + int x, int y, + int first_mb_in_slice, + int last_mb_in_slice, + int first_mb_in_slice_group, + int last_mb_in_slice_group, + int qp_scale_code, + unsigned char target_size_in_word, + unsigned char max_size_in_word, + struct intel_batchbuffer *batch) { VAEncPictureParameterBufferMPEG2 *pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; int len_in_dwords = 9; @@ -704,9 +704,9 @@ gen7_mfc_mpeg2_pak_object_inter(VADriverContextP ctx, static void gen7_mfc_mpeg2_pipeline_header_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - struct intel_batchbuffer *slice_batch) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + struct intel_batchbuffer *slice_batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderMPEG2_SPS); @@ -758,11 +758,11 @@ gen7_mfc_mpeg2_pipeline_header_programing(VADriverContextP ctx, static void gen7_mfc_mpeg2_pipeline_slice_group(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int slice_index, - VAEncSliceParameterBufferMPEG2 *next_slice_group_param, - struct intel_batchbuffer *slice_batch) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + int slice_index, + VAEncSliceParameterBufferMPEG2 *next_slice_group_param, + struct intel_batchbuffer *slice_batch) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -794,16 +794,16 @@ gen7_mfc_mpeg2_pipeline_slice_group(VADriverContextP ctx, } gen7_mfc_mpeg2_slicegroup_state(ctx, - encoder_context, - h_start_pos, - v_start_pos, - h_next_start_pos, - v_next_start_pos, - slice_index == 0, - next_slice_group_param == NULL, - slice_param->is_intra_slice, - slice_param->quantiser_scale_code, - slice_batch); + encoder_context, + h_start_pos, + v_start_pos, + h_next_start_pos, + v_next_start_pos, + slice_index == 0, + next_slice_group_param == NULL, + slice_param->is_intra_slice, + slice_param->quantiser_scale_code, + slice_batch); if (slice_index == 0) gen7_mfc_mpeg2_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); @@ -833,36 +833,36 @@ gen7_mfc_mpeg2_pipeline_slice_group(VADriverContextP ctx, if (slice_param->is_intra_slice) { gen7_mfc_mpeg2_pak_object_intra(ctx, - encoder_context, - h_pos, v_pos, - first_mb_in_slice, - last_mb_in_slice, - first_mb_in_slice_group, - last_mb_in_slice_group, - 0x1a, - slice_param->quantiser_scale_code, - 0x3f, - 0, - 0xff, - slice_batch); + encoder_context, + h_pos, v_pos, + first_mb_in_slice, + last_mb_in_slice, + first_mb_in_slice_group, + last_mb_in_slice_group, + 0x1a, + slice_param->quantiser_scale_code, + 0x3f, + 0, + 0xff, + slice_batch); } else { msg = (unsigned int *)(msg_ptr + (slice_param->macroblock_address + j) * vme_context->vme_output.size_block); if(msg[32] & INTRA_MB_FLAG_MASK) { - gen7_mfc_mpeg2_pak_object_intra(ctx, - encoder_context, - h_pos, v_pos, - first_mb_in_slice, - last_mb_in_slice, - first_mb_in_slice_group, - last_mb_in_slice_group, - 0x1a, - slice_param->quantiser_scale_code, - 0x3f, - 0, - 0xff, - slice_batch); - } else { + gen7_mfc_mpeg2_pak_object_intra(ctx, + encoder_context, + h_pos, v_pos, + first_mb_in_slice, + last_mb_in_slice, + first_mb_in_slice_group, + last_mb_in_slice_group, + 0x1a, + slice_param->quantiser_scale_code, + 0x3f, + 0, + 0xff, + slice_batch); + } else { gen7_mfc_mpeg2_pak_object_inter(ctx, encode_state, @@ -878,8 +878,8 @@ gen7_mfc_mpeg2_pipeline_slice_group(VADriverContextP ctx, 0, 0xff, slice_batch); - } - } + } + } } slice_param++; @@ -920,8 +920,8 @@ gen7_mfc_mpeg2_pipeline_slice_group(VADriverContextP ctx, */ static dri_bo * gen7_mfc_mpeg2_software_slice_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch; @@ -961,8 +961,8 @@ gen7_mfc_mpeg2_software_slice_batchbuffer(VADriverContextP ctx, static void gen7_mfc_mpeg2_pipeline_picture_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -978,8 +978,8 @@ gen7_mfc_mpeg2_pipeline_picture_programing(VADriverContextP ctx, static void gen7_mfc_mpeg2_pipeline_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; dri_bo *slice_batch_bo; @@ -1009,8 +1009,8 @@ gen7_mfc_mpeg2_pipeline_programing(VADriverContextP ctx, static VAStatus gen7_mfc_mpeg2_prepare(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct object_surface *obj_surface; @@ -1084,8 +1084,8 @@ gen7_mfc_mpeg2_prepare(VADriverContextP ctx, static VAStatus gen7_mfc_mpeg2_encode_picture(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { gen6_mfc_init(ctx, encode_state, encoder_context); gen7_mfc_mpeg2_prepare(ctx, encode_state, encoder_context); diff --git a/src/gen7_vme.c b/src/gen7_vme.c index 097fe08b..e6de3af1 100644 --- a/src/gen7_vme.c +++ b/src/gen7_vme.c @@ -267,36 +267,36 @@ gen7_vme_surface_setup(VADriverContextP ctx, slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); if (slice_type == SLICE_TYPE_P || slice_type == SLICE_TYPE_B) { - slice_obj_surface = NULL; - ref_surface_id = slice_param->RefPicList0[0].picture_id; - if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { - slice_obj_surface = SURFACE(ref_surface_id); - } - if (slice_obj_surface && slice_obj_surface->bo) { - obj_surface = slice_obj_surface; - } else { - obj_surface = encode_state->reference_objects[0]; - } - /* reference 0 */ - if (obj_surface && obj_surface->bo) - gen7_vme_source_surface_state(ctx, 1, obj_surface, encoder_context); + slice_obj_surface = NULL; + ref_surface_id = slice_param->RefPicList0[0].picture_id; + if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { + slice_obj_surface = SURFACE(ref_surface_id); + } + if (slice_obj_surface && slice_obj_surface->bo) { + obj_surface = slice_obj_surface; + } else { + obj_surface = encode_state->reference_objects[0]; + } + /* reference 0 */ + if (obj_surface && obj_surface->bo) + gen7_vme_source_surface_state(ctx, 1, obj_surface, encoder_context); } if (slice_type == SLICE_TYPE_B) { - /* reference 1 */ - slice_obj_surface = NULL; - ref_surface_id = slice_param->RefPicList1[0].picture_id; - if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { - slice_obj_surface = SURFACE(ref_surface_id); - } - if (slice_obj_surface && slice_obj_surface->bo) { - obj_surface = slice_obj_surface; - } else { - obj_surface = encode_state->reference_objects[0]; - } - - obj_surface = encode_state->reference_objects[1]; - if (obj_surface && obj_surface->bo) - gen7_vme_source_surface_state(ctx, 2, obj_surface, encoder_context); + /* reference 1 */ + slice_obj_surface = NULL; + ref_surface_id = slice_param->RefPicList1[0].picture_id; + if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) { + slice_obj_surface = SURFACE(ref_surface_id); + } + if (slice_obj_surface && slice_obj_surface->bo) { + obj_surface = slice_obj_surface; + } else { + obj_surface = encode_state->reference_objects[0]; + } + + obj_surface = encode_state->reference_objects[1]; + if (obj_surface && obj_surface->bo) + gen7_vme_source_surface_state(ctx, 2, obj_surface, encoder_context); } } @@ -400,11 +400,11 @@ static VAStatus gen7_vme_avc_state_setup(VADriverContextP ctx, { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned int *vme_state_message; - unsigned int *mb_cost_table; + unsigned int *mb_cost_table; int i; VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; - mb_cost_table = (unsigned int *)vme_context->vme_state_message; + mb_cost_table = (unsigned int *)vme_context->vme_state_message; //building VME state message dri_bo_map(vme_context->vme_state.bo, 1); assert(vme_context->vme_state.bo->virtual); @@ -412,36 +412,36 @@ static VAStatus gen7_vme_avc_state_setup(VADriverContextP ctx, if ((slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP)) { - vme_state_message[0] = 0x01010101; - vme_state_message[1] = 0x10010101; - vme_state_message[2] = 0x0F0F0F0F; - vme_state_message[3] = 0x100F0F0F; - vme_state_message[4] = 0x01010101; - vme_state_message[5] = 0x10010101; - vme_state_message[6] = 0x0F0F0F0F; - vme_state_message[7] = 0x100F0F0F; - vme_state_message[8] = 0x01010101; - vme_state_message[9] = 0x10010101; - vme_state_message[10] = 0x0F0F0F0F; - vme_state_message[11] = 0x000F0F0F; - vme_state_message[12] = 0x00; - vme_state_message[13] = 0x00; - } else { - vme_state_message[0] = 0x10010101; - vme_state_message[1] = 0x100F0F0F; - vme_state_message[2] = 0x10010101; - vme_state_message[3] = 0x000F0F0F; - vme_state_message[4] = 0; - vme_state_message[5] = 0; - vme_state_message[6] = 0; - vme_state_message[7] = 0; - vme_state_message[8] = 0; - vme_state_message[9] = 0; - vme_state_message[10] = 0; - vme_state_message[11] = 0; - vme_state_message[12] = 0; - vme_state_message[13] = 0; - } + vme_state_message[0] = 0x01010101; + vme_state_message[1] = 0x10010101; + vme_state_message[2] = 0x0F0F0F0F; + vme_state_message[3] = 0x100F0F0F; + vme_state_message[4] = 0x01010101; + vme_state_message[5] = 0x10010101; + vme_state_message[6] = 0x0F0F0F0F; + vme_state_message[7] = 0x100F0F0F; + vme_state_message[8] = 0x01010101; + vme_state_message[9] = 0x10010101; + vme_state_message[10] = 0x0F0F0F0F; + vme_state_message[11] = 0x000F0F0F; + vme_state_message[12] = 0x00; + vme_state_message[13] = 0x00; + } else { + vme_state_message[0] = 0x10010101; + vme_state_message[1] = 0x100F0F0F; + vme_state_message[2] = 0x10010101; + vme_state_message[3] = 0x000F0F0F; + vme_state_message[4] = 0; + vme_state_message[5] = 0; + vme_state_message[6] = 0; + vme_state_message[7] = 0; + vme_state_message[8] = 0; + vme_state_message[9] = 0; + vme_state_message[10] = 0; + vme_state_message[11] = 0; + vme_state_message[12] = 0; + vme_state_message[13] = 0; + } vme_state_message[14] = (mb_cost_table[2] & 0xFFFF); vme_state_message[15] = 0; @@ -459,9 +459,9 @@ static VAStatus gen7_vme_avc_state_setup(VADriverContextP ctx, } static VAStatus gen7_vme_mpeg2_state_setup(VADriverContextP ctx, - struct encode_state *encode_state, - int is_intra, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + int is_intra, + struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned int *vme_state_message; @@ -635,8 +635,8 @@ static void gen7_vme_pipeline_programing(VADriverContextP ctx, for (s = 0; s < encode_state->num_slice_params_ext; s++) { pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer; if ((pSliceParameter->macroblock_address % width_in_mbs)) { - allow_hwscore = false; - break; + allow_hwscore = false; + break; } } @@ -644,29 +644,29 @@ static void gen7_vme_pipeline_programing(VADriverContextP ctx, (pSliceParameter->slice_type == SLICE_TYPE_I)) { kernel_shader = AVC_VME_INTRA_SHADER; } else if ((pSliceParameter->slice_type == SLICE_TYPE_P) || - (pSliceParameter->slice_type == SLICE_TYPE_SP)) { + (pSliceParameter->slice_type == SLICE_TYPE_SP)) { kernel_shader = AVC_VME_INTER_SHADER; } else { kernel_shader = AVC_VME_BINTER_SHADER; if (!allow_hwscore) - kernel_shader = AVC_VME_INTER_SHADER; + kernel_shader = AVC_VME_INTER_SHADER; } if (allow_hwscore) gen7_vme_walker_fill_vme_batchbuffer(ctx, - encode_state, - width_in_mbs, height_in_mbs, - kernel_shader, - pPicParameter->pic_fields.bits.transform_8x8_mode_flag, - encoder_context); + encode_state, + width_in_mbs, height_in_mbs, + kernel_shader, + pPicParameter->pic_fields.bits.transform_8x8_mode_flag, + encoder_context); else gen7_vme_fill_vme_batchbuffer(ctx, - encode_state, - width_in_mbs, height_in_mbs, - kernel_shader, - pPicParameter->pic_fields.bits.transform_8x8_mode_flag, - encoder_context); + encode_state, + width_in_mbs, height_in_mbs, + kernel_shader, + pPicParameter->pic_fields.bits.transform_8x8_mode_flag, + encoder_context); intel_batchbuffer_start_atomic(batch, 0x1000); gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch); @@ -692,7 +692,7 @@ static VAStatus gen7_vme_prepare(VADriverContextP ctx, struct gen6_vme_context *vme_context = encoder_context->vme_context; if (!vme_context->h264_level || - (vme_context->h264_level != pSequenceParameter->level_idc)) { + (vme_context->h264_level != pSequenceParameter->level_idc)) { vme_context->h264_level = pSequenceParameter->level_idc; } @@ -743,10 +743,10 @@ gen7_vme_pipeline(VADriverContextP ctx, static void gen7_vme_mpeg2_output_buffer_setup(VADriverContextP ctx, - struct encode_state *encode_state, - int index, - int is_intra, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + int index, + int is_intra, + struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); @@ -777,9 +777,9 @@ gen7_vme_mpeg2_output_buffer_setup(VADriverContextP ctx, static void gen7_vme_mpeg2_output_vme_batchbuffer_setup(VADriverContextP ctx, - struct encode_state *encode_state, - int index, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + int index, + struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); @@ -804,9 +804,9 @@ gen7_vme_mpeg2_output_vme_batchbuffer_setup(VADriverContextP ctx, static VAStatus gen7_vme_mpeg2_surface_setup(VADriverContextP ctx, - struct encode_state *encode_state, - int is_intra, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + int is_intra, + struct intel_encoder_context *encoder_context) { struct object_surface *obj_surface; @@ -837,11 +837,11 @@ gen7_vme_mpeg2_surface_setup(VADriverContextP ctx, static void gen7_vme_mpeg2_fill_vme_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - int mb_width, int mb_height, - int kernel, - int transform_8x8_mode_flag, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + int mb_width, int mb_height, + int kernel, + int transform_8x8_mode_flag, + struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int number_mb_cmds; @@ -909,9 +909,9 @@ gen7_vme_mpeg2_fill_vme_batchbuffer(VADriverContextP ctx, static void gen7_vme_mpeg2_pipeline_programing(VADriverContextP ctx, - struct encode_state *encode_state, - int is_intra, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + int is_intra, + struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct intel_batchbuffer *batch = encoder_context->base.batch; @@ -936,17 +936,17 @@ gen7_vme_mpeg2_pipeline_programing(VADriverContextP ctx, if (allow_hwscore) gen7_vme_mpeg2_walker_fill_vme_batchbuffer(ctx, - encode_state, - width_in_mbs, height_in_mbs, - MPEG2_VME_INTER_SHADER, - encoder_context); + encode_state, + width_in_mbs, height_in_mbs, + MPEG2_VME_INTER_SHADER, + encoder_context); else gen7_vme_mpeg2_fill_vme_batchbuffer(ctx, - encode_state, - width_in_mbs, height_in_mbs, - MPEG2_VME_INTER_SHADER, - 0, - encoder_context); + encode_state, + width_in_mbs, height_in_mbs, + MPEG2_VME_INTER_SHADER, + 0, + encoder_context); intel_batchbuffer_start_atomic(batch, 0x1000); gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch); @@ -963,15 +963,15 @@ gen7_vme_mpeg2_pipeline_programing(VADriverContextP ctx, static VAStatus gen7_vme_mpeg2_prepare(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { VAStatus vaStatus = VA_STATUS_SUCCESS; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; struct gen6_vme_context *vme_context = encoder_context->vme_context; if ((!vme_context->mpeg2_level) || - (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) { + (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) { vme_context->mpeg2_level = seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK; } @@ -991,34 +991,34 @@ gen7_vme_mpeg2_prepare(VADriverContextP ctx, static VAStatus gen7_vme_mpeg2_pipeline(VADriverContextP ctx, - VAProfile profile, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + VAProfile profile, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer; VAEncSequenceParameterBufferMPEG2 *seq_param = - (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; + (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; /*No need of to exec VME for Intra slice */ if (slice_param->is_intra_slice) { - if(!vme_context->vme_output.bo) { - int w_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; - int h_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; - - vme_context->vme_output.num_blocks = w_in_mbs * h_in_mbs; - vme_context->vme_output.pitch = 16; /* in bytes, always 16 */ - vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES; - vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr, - "MPEG2 VME output buffer", - vme_context->vme_output.num_blocks - * vme_context->vme_output.size_block, - 0x1000); - } - - return VA_STATUS_SUCCESS; + if(!vme_context->vme_output.bo) { + int w_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; + int h_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; + + vme_context->vme_output.num_blocks = w_in_mbs * h_in_mbs; + vme_context->vme_output.pitch = 16; /* in bytes, always 16 */ + vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES; + vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr, + "MPEG2 VME output buffer", + vme_context->vme_output.num_blocks + * vme_context->vme_output.size_block, + 0x1000); + } + + return VA_STATUS_SUCCESS; } gen7_vme_media_init(ctx, encoder_context); @@ -1059,7 +1059,7 @@ Bool gen7_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *e struct i965_kernel *vme_kernel_list = NULL; vme_context->gpe_context.surface_state_binding_table.length = - (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; + (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6; vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data); |