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authorWang Tiatian <tiantian.wang@intel.com>2017-09-08 11:01:46 -0400
committerXiang, Haihao <haihao.xiang@intel.com>2017-09-22 16:27:58 +0800
commit75b3c4ac12d63e2e0427f9b4a57a640d580c2fc9 (patch)
tree5ef5136c9e1873879d1a5edf4ab089a1bf120d5c /src/gen9_hevc_encoder.c
parentaca3500581d2e2eefded7263e81314cb66132877 (diff)
downloadlibva-intel-driver-75b3c4ac12d63e2e0427f9b4a57a640d580c2fc9.tar.gz
change prefix of function name from gen9 to i965 in gpe utils
Signed-off-by: Wang Tiatian <tiantian.wang@intel.com>
Diffstat (limited to 'src/gen9_hevc_encoder.c')
-rw-r--r--src/gen9_hevc_encoder.c40
1 files changed, 20 insertions, 20 deletions
diff --git a/src/gen9_hevc_encoder.c b/src/gen9_hevc_encoder.c
index e89b284d..80d9d9c1 100644
--- a/src/gen9_hevc_encoder.c
+++ b/src/gen9_hevc_encoder.c
@@ -794,7 +794,7 @@ gen9_hevc_set_gpe_1d_surface(VADriverContextP ctx,
}
if (gpe_buffer)
- gen9_add_buffer_gpe_surface(ctx, gpe_context,
+ i965_add_buffer_gpe_surface(ctx, gpe_context,
gpe_buffer, is_raw_buffer,
size == 0 ? gpe_buffer->size - offset : size,
offset, bti_idx);
@@ -823,20 +823,20 @@ gen9_hevc_set_gpe_2d_surface(VADriverContextP ctx,
}
if (gpe_buffer) {
- gen9_add_buffer_2d_gpe_surface(ctx,
+ i965_add_buffer_2d_gpe_surface(ctx,
gpe_context,
gpe_buffer,
is_media_block_rw,
format,
bti_idx);
} else if (surface_object) {
- gen9_add_2d_gpe_surface(ctx, gpe_context,
+ i965_add_2d_gpe_surface(ctx, gpe_context,
surface_object,
0, is_media_block_rw, format,
bti_idx);
if (has_uv_surface)
- gen9_add_2d_gpe_surface(ctx, gpe_context,
+ i965_add_2d_gpe_surface(ctx, gpe_context,
surface_object,
1, is_media_block_rw, format,
bti_idx + 1);
@@ -855,7 +855,7 @@ gen9_hevc_set_gpe_adv_surface(VADriverContextP ctx,
surface_object = priv_ctx->gpe_surfaces[surface_type].surface_object;
if (surface_object)
- gen9_add_adv_gpe_surface(ctx, gpe_context,
+ i965_add_adv_gpe_surface(ctx, gpe_context,
surface_object, bti_idx);
}
@@ -3099,12 +3099,12 @@ gen9_hevc_scaling_set_surfaces(VADriverContextP ctx,
else
surface_format = I965_SURFACEFORMAT_R8_UNORM;
- gen9_add_2d_gpe_surface(ctx, gpe_context,
+ i965_add_2d_gpe_surface(ctx, gpe_context,
scaling_param->input_surface,
0, 1, surface_format,
GEN9_HEVC_SCALING_FRAME_SRC_Y_INDEX);
- gen9_add_2d_gpe_surface(ctx, gpe_context,
+ i965_add_2d_gpe_surface(ctx, gpe_context,
scaling_param->output_surface,
0, 1, surface_format,
GEN9_HEVC_SCALING_FRAME_DST_Y_INDEX);
@@ -3113,7 +3113,7 @@ gen9_hevc_scaling_set_surfaces(VADriverContextP ctx,
scaling_param->enable_mb_variance_output ||
scaling_param->enable_mb_pixel_average_output) &&
scaling_param->use_4x_scaling) {
- gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
scaling_param->pres_mbv_proc_stat_buffer,
1,
I965_SURFACEFORMAT_R8_UNORM,
@@ -3404,26 +3404,26 @@ gen9_hevc_me_set_surfaces(VADriverContextP ctx,
switch (hme_type) {
case HEVC_HME_4X:
scaled_surf_id = HEVC_SCALED_SURF_4X_ID;
- gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
&priv_ctx->s4x_memv_data_buffer,
1,
I965_SURFACEFORMAT_R8_UNORM,
GEN9_HEVC_ME_MV_DATA_SURFACE_INDEX);
if (generic_state->b16xme_enabled)
- gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
&priv_ctx->s16x_memv_data_buffer,
1,
I965_SURFACEFORMAT_R8_UNORM,
GEN9_HEVC_ME_16X_MV_DATA_SURFACE_INDEX);
- gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
&priv_ctx->res_brc_me_dist_buffer,
1,
I965_SURFACEFORMAT_R8_UNORM,
GEN9_HEVC_ME_BRC_DISTORTION_INDEX);
- gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
&priv_ctx->s4x_memv_distortion_buffer,
1,
I965_SURFACEFORMAT_R8_UNORM,
@@ -3432,20 +3432,20 @@ gen9_hevc_me_set_surfaces(VADriverContextP ctx,
case HEVC_HME_16X:
scaled_surf_id = HEVC_SCALED_SURF_16X_ID;
- gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
&priv_ctx->s16x_memv_data_buffer,
1,
I965_SURFACEFORMAT_R8_UNORM,
GEN9_HEVC_ME_MV_DATA_SURFACE_INDEX);
if (generic_state->b32xme_enabled)
- gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
&priv_ctx->s32x_memv_data_buffer,
1,
I965_SURFACEFORMAT_R8_UNORM,
GEN9_HEVC_ME_32X_MV_DATA_SURFACE_INDEX);
else
- gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
&priv_ctx->s16x_memv_data_buffer,
1,
I965_SURFACEFORMAT_R8_UNORM,
@@ -3453,7 +3453,7 @@ gen9_hevc_me_set_surfaces(VADriverContextP ctx,
break;
case HEVC_HME_32X:
scaled_surf_id = HEVC_SCALED_SURF_32X_ID;
- gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
&priv_ctx->s32x_memv_data_buffer,
1,
I965_SURFACEFORMAT_R8_UNORM,
@@ -3465,7 +3465,7 @@ gen9_hevc_me_set_surfaces(VADriverContextP ctx,
obj_surface = encode_state->reconstructed_object;
surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
- gen9_add_adv_gpe_surface(ctx, gpe_context,
+ i965_add_adv_gpe_surface(ctx, gpe_context,
surface_priv->scaled_surface_obj[scaled_surf_id],
GEN9_HEVC_ME_CURR_FOR_FWD_REF_INDEX);
@@ -3476,14 +3476,14 @@ gen9_hevc_me_set_surfaces(VADriverContextP ctx,
break;
surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
- gen9_add_adv_gpe_surface(ctx, gpe_context,
+ i965_add_adv_gpe_surface(ctx, gpe_context,
surface_priv->scaled_surface_obj[scaled_surf_id],
GEN9_HEVC_ME_CURR_FOR_FWD_REF_INDEX + i * 2 + 1);
}
obj_surface = encode_state->reconstructed_object;
surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
- gen9_add_adv_gpe_surface(ctx, gpe_context,
+ i965_add_adv_gpe_surface(ctx, gpe_context,
surface_priv->scaled_surface_obj[scaled_surf_id],
GEN9_HEVC_ME_CURR_FOR_BWD_REF_INDEX);
@@ -3494,7 +3494,7 @@ gen9_hevc_me_set_surfaces(VADriverContextP ctx,
break;
surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
- gen9_add_adv_gpe_surface(ctx, gpe_context,
+ i965_add_adv_gpe_surface(ctx, gpe_context,
surface_priv->scaled_surface_obj[scaled_surf_id],
GEN9_HEVC_ME_CURR_FOR_BWD_REF_INDEX + i * 2 + 1);
}