diff options
| author | Mark Thompson <sw@jkqxz.net> | 2017-01-10 00:04:43 +0000 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2017-01-10 08:59:16 +0800 |
| commit | f804a502699c05b6a61afac833fd465df16b32c8 (patch) | |
| tree | cda025fc5d21b00616b93ad3f38df4ba555129ab /src/gen75_mfc.c | |
| parent | ecde5e89a8e3e8567fc95e5a3af22834583b5778 (diff) | |
| download | libva-intel-driver-f804a502699c05b6a61afac833fd465df16b32c8.tar.gz | |
H.264 encoder: add a simple reactive VBR rate control mode
This implements a simple reactive VBR rate control mode for single-layer H.264.
The primary aim here is to avoid the problematic behaviour that the CBR rate
controller displays on scene changes, where the QP can get pushed up by a large
amount in a short period and compromise the quality of following frames to a
very visible degree.
The main idea, then, is to try to keep the HRD buffering above the target level
most of the time, so that when a large frame is generated (on a scene change or
when the stream complexity increases) we have plenty of slack to be able to
encode the more difficult region without compromising quality immediately on
the following frames. It is optimistic about the complexity of future frames,
so even after generating one or more large frames on a significant change it
will try to keep the QP at its current level until the HRD buffer bounds force
a change to maintain the intended rate.
Compared to the CBR rate controller, it keeps the quality level much more
stable - QP does not always spike up as large frames are generated when the
complexity of the stream increases transiently, but equally it does not reduce
as quickly when the complexity of the stream decreases.
Signed-off-by: Mark Thompson <sw@jkqxz.net>
Diffstat (limited to 'src/gen75_mfc.c')
| -rw-r--r-- | src/gen75_mfc.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/gen75_mfc.c b/src/gen75_mfc.c index 0fbbe76f..7b76b991 100644 --- a/src/gen75_mfc.c +++ b/src/gen75_mfc.c @@ -1174,7 +1174,7 @@ gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, int qp_mb; qp_slice = qp; - if (rate_control_mode == VA_RC_CBR) { + if (rate_control_mode != VA_RC_CQP) { qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type]; if (encode_state->slice_header_index[slice_index] == 0) { pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp; @@ -1192,7 +1192,7 @@ gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, pPicParameter, pSliceParameter, encode_state, encoder_context, - (rate_control_mode == VA_RC_CBR), qp_slice, slice_batch); + (rate_control_mode != VA_RC_CQP), qp_slice, slice_batch); if ( slice_index == 0) intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); @@ -1521,7 +1521,7 @@ gen75_mfc_avc_batchbuffer_slice(VADriverContextP ctx, int qp_slice; qp_slice = qp; - if (rate_control_mode == VA_RC_CBR) { + if (rate_control_mode != VA_RC_CQP) { qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type]; if (encode_state->slice_header_index[slice_index] == 0) { pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp; @@ -1540,7 +1540,7 @@ gen75_mfc_avc_batchbuffer_slice(VADriverContextP ctx, pSliceParameter, encode_state, encoder_context, - (rate_control_mode == VA_RC_CBR), + (rate_control_mode != VA_RC_CQP), qp_slice, slice_batch); @@ -1702,7 +1702,7 @@ gen75_mfc_avc_encode_picture(VADriverContextP ctx, /*Programing bcs pipeline*/ gen75_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline gen75_mfc_run(ctx, encode_state, encoder_context); - if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) { + if (rate_control_mode == VA_RC_CBR || rate_control_mode == VA_RC_VBR) { gen75_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size); sts = intel_mfc_brc_postpack(encode_state, encoder_context, current_frame_bits_size); if (sts == BRC_NO_HRD_VIOLATION) { |