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| author | Xiang, Haihao <haihao.xiang@intel.com> | 2017-10-20 08:07:25 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2017-12-19 15:02:41 +0800 |
| commit | 05d797e912bbdf6d8795b8a79aed34e36317b8d2 (patch) | |
| tree | ab271fee6eb033041dae4110725446bbe2437974 | |
| parent | 1346c190ab8254a28770070914e343bd593f1eeb (diff) | |
| download | libva-intel-driver-05d797e912bbdf6d8795b8a79aed34e36317b8d2.tar.gz | |
Do CSC/scaling for YV12/IMC1/IMC3 surface in the common path
The existing vpp shader is re-used
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
| -rw-r--r-- | src/gen8_post_processing.c | 16 | ||||
| -rw-r--r-- | src/gen9_post_processing.c | 21 | ||||
| -rw-r--r-- | src/intel_common_vpp_internal.c | 10 |
3 files changed, 32 insertions, 15 deletions
diff --git a/src/gen8_post_processing.c b/src/gen8_post_processing.c index 449545e9..93afd490 100644 --- a/src/gen8_post_processing.c +++ b/src/gen8_post_processing.c @@ -1904,7 +1904,6 @@ gen8_pp_context_get_surface_conf(VADriverContextP ctx, pitch[1] = obj_surface->cb_cr_pitch; bo_offset[1] = obj_surface->width * obj_surface->y_cb_offset; } else { - /* I010/I420 format */ width[1] = width[0] / 2; height[1] = height[0] / 2; pitch[1] = obj_surface->cb_cr_pitch; @@ -1931,16 +1930,19 @@ gen8_pp_context_get_surface_conf(VADriverContextP ctx, pitch[1] = obj_image->image.pitches[1]; bo_offset[1] = obj_image->image.offsets[1]; } else { - /* I010/I420 format */ - /* YV12 is TBD */ + int u = 1, v = 2; + + if (fourcc == VA_FOURCC_YV12 || fourcc == VA_FOURCC_IMC1) + u = 2, v = 1; + width[1] = width[0] / 2; height[1] = height[0] / 2; - pitch[1] = obj_image->image.pitches[1]; - bo_offset[1] = obj_image->image.offsets[1]; + pitch[1] = obj_image->image.pitches[u]; + bo_offset[1] = obj_image->image.offsets[u]; width[2] = width[0] / 2; height[2] = height[0] / 2; - pitch[2] = obj_image->image.pitches[2]; - bo_offset[2] = obj_image->image.offsets[2]; + pitch[2] = obj_image->image.pitches[v]; + bo_offset[2] = obj_image->image.offsets[v]; } } diff --git a/src/gen9_post_processing.c b/src/gen9_post_processing.c index 02f825d2..98b50f00 100644 --- a/src/gen9_post_processing.c +++ b/src/gen9_post_processing.c @@ -720,7 +720,6 @@ gen9_pp_context_get_surface_conf(VADriverContextP ctx, } else if (fourcc == VA_FOURCC_YUY2 || fourcc == VA_FOURCC_UYVY) { /* nothing to do here */ } else { - /* I010/I420 format */ width[1] = width[0] / 2; height[1] = height[0] / 2; pitch[1] = obj_surface->cb_cr_pitch; @@ -749,15 +748,19 @@ gen9_pp_context_get_surface_conf(VADriverContextP ctx, } else if (fourcc == VA_FOURCC_YUY2 || fourcc == VA_FOURCC_UYVY) { /* nothing to do here */ } else { - /* I010/I420 format */ + int u = 1, v = 2; + + if (fourcc == VA_FOURCC_YV12 || fourcc == VA_FOURCC_IMC1) + u = 2, v = 1; + width[1] = width[0] / 2; height[1] = height[0] / 2; - pitch[1] = obj_image->image.pitches[1]; - bo_offset[1] = obj_image->image.offsets[1]; + pitch[1] = obj_image->image.pitches[u]; + bo_offset[1] = obj_image->image.offsets[u]; width[2] = width[0] / 2; height[2] = height[0] / 2; - pitch[2] = obj_image->image.pitches[2]; - bo_offset[2] = obj_image->image.offsets[2]; + pitch[2] = obj_image->image.pitches[v]; + bo_offset[2] = obj_image->image.offsets[v]; } } @@ -1233,9 +1236,15 @@ gen9_gpe_context_10bit_8bit_scaling_curbe(VADriverContextP ctx, break; case VA_FOURCC_I420: + case VA_FOURCC_IMC3: /* pitch / base address is set via surface_state */ dst_format = DST_FORMAT_I420; break; + case VA_FOURCC_YV12: + case VA_FOURCC_IMC1: /* pitch / base address is set via surface_state */ + dst_format = DST_FORMAT_YV12; + break; + default: break; } diff --git a/src/intel_common_vpp_internal.c b/src/intel_common_vpp_internal.c index 12ac33ed..ca3e6318 100644 --- a/src/intel_common_vpp_internal.c +++ b/src/intel_common_vpp_internal.c @@ -136,7 +136,10 @@ intel_common_scaling_post_processing(VADriverContextP ctx, scale_flag |= SRC_10BIT_420; if (src_fourcc == VA_FOURCC_NV12 || - src_fourcc == VA_FOURCC_I420) + src_fourcc == VA_FOURCC_I420 || + src_fourcc == VA_FOURCC_IMC3 || + src_fourcc == VA_FOURCC_YV12 || + src_fourcc == VA_FOURCC_IMC1) scale_flag |= SRC_8BIT_420; if (src_fourcc == VA_FOURCC_YUY2 || @@ -148,7 +151,10 @@ intel_common_scaling_post_processing(VADriverContextP ctx, scale_flag |= DST_10BIT_420; if (dst_fourcc == VA_FOURCC_NV12 || - dst_fourcc == VA_FOURCC_I420) + dst_fourcc == VA_FOURCC_I420 || + dst_fourcc == VA_FOURCC_IMC3 || + dst_fourcc == VA_FOURCC_YV12 || + dst_fourcc == VA_FOURCC_IMC1) scale_flag |= DST_8BIT_420; if (dst_fourcc == VA_FOURCC_YUY2 || |