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| author | Adeel Mujahid <3840695+am11@users.noreply.github.com> | 2022-08-05 03:14:42 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-04 20:14:42 -0400 |
| commit | 14e199e1f2edeecc5789e3ce10dbd5de7fd86441 (patch) | |
| tree | fd2abf68218469cad11dd9bc8f28f451a76f185b /doc/libunwind-dynamic.tex | |
| parent | 919da2e0c42e6e4a3b3da63001863e586787fab4 (diff) | |
| download | libunwind-14e199e1f2edeecc5789e3ce10dbd5de7fd86441.tar.gz | |
Fix typos (#397)
* Fix typos
* Cleanup trailing whitespaces in committed files
* Update include/tdep-ia64/libunwind_i.h
Diffstat (limited to 'doc/libunwind-dynamic.tex')
| -rw-r--r-- | doc/libunwind-dynamic.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/doc/libunwind-dynamic.tex b/doc/libunwind-dynamic.tex index f3258921..a3b7762b 100644 --- a/doc/libunwind-dynamic.tex +++ b/doc/libunwind-dynamic.tex @@ -78,7 +78,7 @@ contrast, most CISC use variable-length instruction encodings, so it is usually necessary to use a byte-offset as the index. Given the instruction index, the operation descriptor specifies the effect of the instruction in an abstract manner. For example, it might express -that the instruction stores calle-saved register \Var{r1} at offset 16 +that the instruction stores callee-saved register \Var{r1} at offset 16 in the stack frame. \section{Procedures} |