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| author | Stef O'Rear <sorear2@gmail.com> | 2018-03-11 05:55:15 -0700 |
|---|---|---|
| committer | Anthony Green <green@moxielogic.com> | 2018-03-11 08:55:15 -0400 |
| commit | 3840d49aaa831d649b1597518a2903dfed0d57f3 (patch) | |
| tree | da49ee49ae31cc6e44beeb59930e995c4ec00ebb /configure.host | |
| parent | dca52b55bc2ac0213c20849d7e9e19fbc9202023 (diff) | |
| download | libffi-3840d49aaa831d649b1597518a2903dfed0d57f3.tar.gz | |
New RISC-V port (#281)
* Add RISC-V support
This patch adds support for the RISC-V architecture (https://riscv.org).
This patch has been tested using QEMU user-mode emulation and GCC 7.2.0
in the following configurations:
* -march=rv32imac -mabi=ilp32
* -march=rv32g -mabi=ilp32d
* -march=rv64imac -mabi=lp64
* -march=rv64g -mabi=lp64d
The ABI currently can be found at
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md .
* Add RISC-V to README
* RISC-V: fix configure.host
Diffstat (limited to 'configure.host')
| -rw-r--r-- | configure.host | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/configure.host b/configure.host index 34e83f7..7634c3a 100644 --- a/configure.host +++ b/configure.host @@ -206,6 +206,11 @@ case "${host}" in TARGET=POWERPC; TARGETDIR=powerpc ;; + riscv*-*) + TARGET=RISCV; TARGETDIR=riscv + SOURCES="ffi.c sysv.S" + ;; + s390-*-* | s390x-*-*) TARGET=S390; TARGETDIR=s390 SOURCES="ffi.c sysv.S" |