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| author | Ben Gamari <ben@smart-cactus.org> | 2019-07-09 14:49:32 -0400 |
|---|---|---|
| committer | Ben Gamari <ben@smart-cactus.org> | 2019-07-13 11:36:29 -0400 |
| commit | 311ec702a78c9e2ba35e66c77e53748e8e751f8d (patch) | |
| tree | 792eb726fbc1c8bdf63e1e43975869c18f85b58f /compiler/nativeGen/SPARC/Regs.hs | |
| parent | de3935a6ccc26ec063e13d2739dd098c7616fde2 (diff) | |
| download | haskell-wip/back-out-simd.tar.gz | |
Revert "Add support for SIMD operations in the NCG"wip/back-out-simd
Unfortunately this will require more work; register allocation is
quite broken.
This reverts commit acd795583625401c5554f8e04ec7efca18814011.
Diffstat (limited to 'compiler/nativeGen/SPARC/Regs.hs')
| -rw-r--r-- | compiler/nativeGen/SPARC/Regs.hs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/compiler/nativeGen/SPARC/Regs.hs b/compiler/nativeGen/SPARC/Regs.hs index e46dbd0d38..0d7edc346a 100644 --- a/compiler/nativeGen/SPARC/Regs.hs +++ b/compiler/nativeGen/SPARC/Regs.hs @@ -104,6 +104,7 @@ virtualRegSqueeze cls vr VirtualRegD{} -> 1 _other -> 0 + {-# INLINE realRegSqueeze #-} realRegSqueeze :: RegClass -> RealReg -> Int @@ -133,6 +134,7 @@ realRegSqueeze cls rr RealRegPair{} -> 1 + -- | All the allocatable registers in the machine, -- including register pairs. allRealRegs :: [RealReg] |