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authorKarel Gardas <karel.gardas@centrum.cz>2012-04-25 09:04:50 +0200
committerSimon Marlow <marlowsd@gmail.com>2012-04-27 11:13:06 +0100
commit3144f85661da176e3d80f28d652b42245becde09 (patch)
treef10ab746a7cf379e134960ca7daaa2c14643a46e /compiler/nativeGen/RegAlloc
parent18c2a2f71e38fad5e677b8f448f6135e5a691868 (diff)
downloadhaskell-3144f85661da176e3d80f28d652b42245becde09.tar.gz
add support for ARM hard-float ABI (fixes #5914)
This patch enhances Platform's ArchARM to include ARM ABI value. It also tweaks configure machinery to detect hard-float ABI and to set it wherever needed. Finally when hard-float ABI is in use, pass appropriate compiler option to the LLVM's llc. Fixes #5914.
Diffstat (limited to 'compiler/nativeGen/RegAlloc')
-rw-r--r--compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs56
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs14
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/Main.hs14
3 files changed, 42 insertions, 42 deletions
diff --git a/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs b/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs
index 6067f23ade..6cd3f00024 100644
--- a/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs
@@ -107,13 +107,13 @@ trivColorable
trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts exclusions
| let !cALLOCATABLE_REGS_INTEGER
= iUnbox (case platformArch platform of
- ArchX86 -> 3
- ArchX86_64 -> 5
- ArchPPC -> 16
- ArchSPARC -> 14
- ArchPPC_64 -> panic "trivColorable ArchPPC_64"
- ArchARM _ _ -> panic "trivColorable ArchARM"
- ArchUnknown -> panic "trivColorable ArchUnknown")
+ ArchX86 -> 3
+ ArchX86_64 -> 5
+ ArchPPC -> 16
+ ArchSPARC -> 14
+ ArchPPC_64 -> panic "trivColorable ArchPPC_64"
+ ArchARM _ _ _ -> panic "trivColorable ArchARM"
+ ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_INTEGER
(virtualRegSqueeze RcInteger)
conflicts
@@ -127,13 +127,13 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts excl
trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclusions
| let !cALLOCATABLE_REGS_FLOAT
= iUnbox (case platformArch platform of
- ArchX86 -> 0
- ArchX86_64 -> 0
- ArchPPC -> 0
- ArchSPARC -> 22
- ArchPPC_64 -> panic "trivColorable ArchPPC_64"
- ArchARM _ _ -> panic "trivColorable ArchARM"
- ArchUnknown -> panic "trivColorable ArchUnknown")
+ ArchX86 -> 0
+ ArchX86_64 -> 0
+ ArchPPC -> 0
+ ArchSPARC -> 22
+ ArchPPC_64 -> panic "trivColorable ArchPPC_64"
+ ArchARM _ _ _ -> panic "trivColorable ArchARM"
+ ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_FLOAT
(virtualRegSqueeze RcFloat)
conflicts
@@ -147,13 +147,13 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclus
trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclusions
| let !cALLOCATABLE_REGS_DOUBLE
= iUnbox (case platformArch platform of
- ArchX86 -> 6
- ArchX86_64 -> 0
- ArchPPC -> 26
- ArchSPARC -> 11
- ArchPPC_64 -> panic "trivColorable ArchPPC_64"
- ArchARM _ _ -> panic "trivColorable ArchARM"
- ArchUnknown -> panic "trivColorable ArchUnknown")
+ ArchX86 -> 6
+ ArchX86_64 -> 0
+ ArchPPC -> 26
+ ArchSPARC -> 11
+ ArchPPC_64 -> panic "trivColorable ArchPPC_64"
+ ArchARM _ _ _ -> panic "trivColorable ArchARM"
+ ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_DOUBLE
(virtualRegSqueeze RcDouble)
conflicts
@@ -167,13 +167,13 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclu
trivColorable platform virtualRegSqueeze realRegSqueeze RcDoubleSSE conflicts exclusions
| let !cALLOCATABLE_REGS_SSE
= iUnbox (case platformArch platform of
- ArchX86 -> 8
- ArchX86_64 -> 10
- ArchPPC -> 0
- ArchSPARC -> 0
- ArchPPC_64 -> panic "trivColorable ArchPPC_64"
- ArchARM _ _ -> panic "trivColorable ArchARM"
- ArchUnknown -> panic "trivColorable ArchUnknown")
+ ArchX86 -> 8
+ ArchX86_64 -> 10
+ ArchPPC -> 0
+ ArchSPARC -> 0
+ ArchPPC_64 -> panic "trivColorable ArchPPC_64"
+ ArchARM _ _ _ -> panic "trivColorable ArchARM"
+ ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_SSE
(virtualRegSqueeze RcDoubleSSE)
conflicts
diff --git a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
index 6fbbd04fff..fd1fd272bd 100644
--- a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
@@ -68,11 +68,11 @@ instance FR SPARC.FreeRegs where
maxSpillSlots :: Platform -> Int
maxSpillSlots platform
= case platformArch platform of
- ArchX86 -> X86.Instr.maxSpillSlots True -- 32bit
- ArchX86_64 -> X86.Instr.maxSpillSlots False -- not 32bit
- ArchPPC -> PPC.Instr.maxSpillSlots
- ArchSPARC -> SPARC.Instr.maxSpillSlots
- ArchARM _ _ -> panic "maxSpillSlots ArchARM"
- ArchPPC_64 -> panic "maxSpillSlots ArchPPC_64"
- ArchUnknown -> panic "maxSpillSlots ArchUnknown"
+ ArchX86 -> X86.Instr.maxSpillSlots True -- 32bit
+ ArchX86_64 -> X86.Instr.maxSpillSlots False -- not 32bit
+ ArchPPC -> PPC.Instr.maxSpillSlots
+ ArchSPARC -> SPARC.Instr.maxSpillSlots
+ ArchARM _ _ _ -> panic "maxSpillSlots ArchARM"
+ ArchPPC_64 -> panic "maxSpillSlots ArchPPC_64"
+ ArchUnknown -> panic "maxSpillSlots ArchUnknown"
diff --git a/compiler/nativeGen/RegAlloc/Linear/Main.hs b/compiler/nativeGen/RegAlloc/Linear/Main.hs
index fc0bde44a0..64b0f68eda 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Main.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Main.hs
@@ -180,13 +180,13 @@ linearRegAlloc
linearRegAlloc dflags first_id block_live sccs
= let platform = targetPlatform dflags
in case platformArch platform of
- ArchX86 -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs) first_id block_live sccs
- ArchX86_64 -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs) first_id block_live sccs
- ArchSPARC -> linearRegAlloc' platform (frInitFreeRegs :: SPARC.FreeRegs) first_id block_live sccs
- ArchPPC -> linearRegAlloc' platform (frInitFreeRegs :: PPC.FreeRegs) first_id block_live sccs
- ArchARM _ _ -> panic "linearRegAlloc ArchARM"
- ArchPPC_64 -> panic "linearRegAlloc ArchPPC_64"
- ArchUnknown -> panic "linearRegAlloc ArchUnknown"
+ ArchX86 -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs) first_id block_live sccs
+ ArchX86_64 -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs) first_id block_live sccs
+ ArchSPARC -> linearRegAlloc' platform (frInitFreeRegs :: SPARC.FreeRegs) first_id block_live sccs
+ ArchPPC -> linearRegAlloc' platform (frInitFreeRegs :: PPC.FreeRegs) first_id block_live sccs
+ ArchARM _ _ _ -> panic "linearRegAlloc ArchARM"
+ ArchPPC_64 -> panic "linearRegAlloc ArchPPC_64"
+ ArchUnknown -> panic "linearRegAlloc ArchUnknown"
linearRegAlloc'
:: (FR freeRegs, PlatformOutputable instr, Instruction instr)
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