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| author | Bartosz Nitka <niteria@gmail.com> | 2016-06-30 08:20:41 -0700 |
|---|---|---|
| committer | Bartosz Nitka <niteria@gmail.com> | 2016-06-30 10:22:41 -0700 |
| commit | 480e0661fb45395610d6b4a7c586a580d30d8df4 (patch) | |
| tree | cc4a0effeaa3a46ea370496fb2a2143448b168f6 /compiler/nativeGen/RegAlloc/Linear/Main.hs | |
| parent | b6b20a5074ad7d712b4d8448043fc25e4c7bcdaa (diff) | |
| download | haskell-480e0661fb45395610d6b4a7c586a580d30d8df4.tar.gz | |
Remove ufmToList
This documents nondeterminism in code generation and removes
the nondeterministic ufmToList function. In the future someone
will have to use nonDetUFMToList (with proper explanation)
or pprUFMWithKeys.
Diffstat (limited to 'compiler/nativeGen/RegAlloc/Linear/Main.hs')
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/Main.hs | 30 |
1 files changed, 21 insertions, 9 deletions
diff --git a/compiler/nativeGen/RegAlloc/Linear/Main.hs b/compiler/nativeGen/RegAlloc/Linear/Main.hs index edb2394954..3e2edc7c97 100644 --- a/compiler/nativeGen/RegAlloc/Linear/Main.hs +++ b/compiler/nativeGen/RegAlloc/Linear/Main.hs @@ -620,7 +620,10 @@ saveClobberedTemps clobbered dying assig <- getAssigR let to_spill = [ (temp,reg) - | (temp, InReg reg) <- ufmToList assig + | (temp, InReg reg) <- nonDetUFMToList assig + -- This is non-deterministic but we do not + -- currently support deterministic code-generation. + -- See Note [Unique Determinism and code generation] , any (realRegsAlias reg) clobbered , temp `notElem` map getUnique dying ] @@ -682,7 +685,10 @@ clobberRegs clobbered setFreeRegsR $! foldr (frAllocateReg platform) freeregs clobbered assig <- getAssigR - setAssigR $! clobber assig (ufmToList assig) + setAssigR $! clobber assig (nonDetUFMToList assig) + -- This is non-deterministic but we do not + -- currently support deterministic code-generation. + -- See Note [Unique Determinism and code generation] where -- if the temp was InReg and clobbered, then we will have @@ -802,17 +808,23 @@ allocRegsAndSpill_spill reading keep spills alloc r rs assig spill_loc -- the vregs we could kick out that are already in a slot let candidates_inBoth = [ (temp, reg, mem) - | (temp, InBoth reg mem) <- ufmToList assig - , temp `notElem` keep' - , targetClassOfRealReg platform reg == classOfVirtualReg r ] + | (temp, InBoth reg mem) <- nonDetUFMToList assig + -- This is non-deterministic but we do not + -- currently support deterministic code-generation. + -- See Note [Unique Determinism and code generation] + , temp `notElem` keep' + , targetClassOfRealReg platform reg == classOfVirtualReg r ] -- the vregs we could kick out that are only in a reg -- this would require writing the reg to a new slot before using it. let candidates_inReg = [ (temp, reg) - | (temp, InReg reg) <- ufmToList assig - , temp `notElem` keep' - , targetClassOfRealReg platform reg == classOfVirtualReg r ] + | (temp, InReg reg) <- nonDetUFMToList assig + -- This is non-deterministic but we do not + -- currently support deterministic code-generation. + -- See Note [Unique Determinism and code generation] + , temp `notElem` keep' + , targetClassOfRealReg platform reg == classOfVirtualReg r ] let result @@ -857,7 +869,7 @@ allocRegsAndSpill_spill reading keep spills alloc r rs assig spill_loc = pprPanic ("RegAllocLinear.allocRegsAndSpill: no spill candidates\n") $ vcat [ text "allocating vreg: " <> text (show r) - , text "assignment: " <> text (show $ ufmToList assig) + , text "assignment: " <> ppr assig , text "freeRegs: " <> text (show freeRegs) , text "initFreeRegs: " <> text (show (frInitFreeRegs platform `asTypeOf` freeRegs)) ] |