Split Reg into vreg/hreg and add register pairs

 * The old Reg type is now split into VirtualReg and RealReg.
 * For the graph coloring allocator, the type of the register graph
   is now (Graph VirtualReg RegClass RealReg), which shows that it colors
   in nodes representing virtual regs with colors representing real regs.
   (as was intended)  
 * RealReg contains two contructors, RealRegSingle and RealRegPair,
   where RealRegPair is used to represent a SPARC double reg 
   constructed from two single precision FP regs. 
 * On SPARC we can now allocate double regs into an arbitrary register
   pair, instead of reserving some reg ranges to only hold float/double values. 

1 files changed, 4 insertions, 4 deletions

diff --git a/compiler/nativeGen/RegAlloc/Linear/Base.hs b/compiler/nativeGen/RegAlloc/Linear/Base.hs
index 45fd640804..26262327c9 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Base.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Base.hs
@@ -51,14 +51,14 @@ type BlockAssignment
 --
 data Loc 
 	-- | vreg is in a register
-	= InReg   {-# UNPACK #-} !RegNo
+	= InReg   {-# UNPACK #-}  !RealReg
 
 	-- | vreg is held in a stack slot
-	| InMem   {-# UNPACK #-} !StackSlot
+	| InMem   {-# UNPACK #-}  !StackSlot
 
 
 	-- | vreg is held in both a register and a stack slot
-	| InBoth  {-# UNPACK #-}  !RegNo
+	| InBoth  {-# UNPACK #-}  !RealReg
 		   {-# UNPACK #-} !StackSlot
 	deriving (Eq, Show, Ord)
 
@@ -67,7 +67,7 @@ instance Outputable Loc where
 
 
 -- | Get the reg numbers stored in this Loc.
-regsOfLoc :: Loc -> [RegNo]
+regsOfLoc :: Loc -> [RealReg]
 regsOfLoc (InReg r)    = [r]
 regsOfLoc (InBoth r _) = [r]
 regsOfLoc (InMem _)    = []