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authorBen Gamari <ben@smart-cactus.org>2019-07-09 14:49:32 -0400
committerMarge Bot <ben+marge-bot@smart-cactus.org>2019-07-16 02:40:43 -0400
commitdb948daea6c01c073f8d09a79fa5adda279fbf0c (patch)
tree50fdb60bdd06a12dab101bf4fca3358fec0ad43d /compiler/llvmGen/LlvmCodeGen/Base.hs
parent5728d9faafe410d1e0c3a070bb8882721470b798 (diff)
downloadhaskell-db948daea6c01c073f8d09a79fa5adda279fbf0c.tar.gz
Revert "Add support for SIMD operations in the NCG"
Unfortunately this will require more work; register allocation is quite broken. This reverts commit acd795583625401c5554f8e04ec7efca18814011.
Diffstat (limited to 'compiler/llvmGen/LlvmCodeGen/Base.hs')
-rw-r--r--compiler/llvmGen/LlvmCodeGen/Base.hs12
1 files changed, 6 insertions, 6 deletions
diff --git a/compiler/llvmGen/LlvmCodeGen/Base.hs b/compiler/llvmGen/LlvmCodeGen/Base.hs
index a5a5683a3e..81f3b9f84c 100644
--- a/compiler/llvmGen/LlvmCodeGen/Base.hs
+++ b/compiler/llvmGen/LlvmCodeGen/Base.hs
@@ -152,12 +152,12 @@ llvmFunArgs dflags live =
where platform = targetPlatform dflags
isLive r = not (isSSE r) || r `elem` alwaysLive || r `elem` live
isPassed r = not (isSSE r) || isLive r
- isSSE (FloatReg _) = True
- isSSE (DoubleReg _) = True
- isSSE (XmmReg _ _ _ _ ) = True
- isSSE (YmmReg _ _ _ _ ) = True
- isSSE (ZmmReg _ _ _ _ ) = True
- isSSE _ = False
+ isSSE (FloatReg _) = True
+ isSSE (DoubleReg _) = True
+ isSSE (XmmReg _) = True
+ isSSE (YmmReg _) = True
+ isSSE (ZmmReg _) = True
+ isSSE _ = False
-- | Llvm standard fun attributes
llvmStdFunAttrs :: [LlvmFuncAttr]