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authorSimon Marlow <marlowsd@gmail.com>2012-09-20 14:12:05 +0100
committerSimon Marlow <marlowsd@gmail.com>2012-09-20 14:12:05 +0100
commitc90d45f2bf1f350a0cc99c60eb81704b25309d53 (patch)
tree6c3ec4959b5db1730fe690725e9ce870f4014c4d
parent096396d980501fb5864a1923e283b07757277734 (diff)
downloadhaskell-c90d45f2bf1f350a0cc99c60eb81704b25309d53.tar.gz
fix warnings
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/StackMap.hs5
1 files changed, 1 insertions, 4 deletions
diff --git a/compiler/nativeGen/RegAlloc/Linear/StackMap.hs b/compiler/nativeGen/RegAlloc/Linear/StackMap.hs
index be9af022f8..69cf411751 100644
--- a/compiler/nativeGen/RegAlloc/Linear/StackMap.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/StackMap.hs
@@ -27,10 +27,7 @@ module RegAlloc.Linear.StackMap (
where
-import RegAlloc.Linear.FreeRegs
-
import DynFlags
-import Outputable
import UniqFM
import Unique
@@ -49,7 +46,7 @@ data StackMap
-- | An empty stack map, with all slots available.
emptyStackMap :: DynFlags -> StackMap
-emptyStackMap dflags = StackMap 0 emptyUFM
+emptyStackMap _ = StackMap 0 emptyUFM
-- | If this vreg unique already has a stack assignment then return the slot number,