cmd/internal/obj: instructions and registers for RISC-V

Start implementing an assembler for RISC-V - this provides register
definitions and instruction mnemonics as defined in the RISC-V
Instruction Set Manual, along with instruction encoding.

The instruction encoding is generated by the parse_opcodes script with
the "opcodes" and "opcodes-pseudo" files from (`make inst.go`):

  https://github.com/riscv/riscv-opcodes

This is based on the riscv-go port:

  https://github.com/riscv/riscv-go

Contributors to the riscv-go port are:

  Amol Bhave <ammubhave@gmail.com>
  Benjamin Barenblat <bbaren@google.com>
  Josh Bleecher Snyder <josharian@gmail.com>
  Michael Pratt <michael@pratt.im>
  Michael Yenik <myenik@google.com>
  Ronald G. Minnich <rminnich@gmail.com>
  Stefan O'Rear <sorear2@gmail.com>

This port has been updated to Go 1.13:

  https://github.com/4a6f656c/riscv-go

Updates #27532

Change-Id: I257b6de87e9864df61a2b0ce9be15968c1227b49
Reviewed-on: https://go-review.googlesource.com/c/go/+/193677
Run-TryBot: Brad Fitzpatrick <bradfitz@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>

5 files changed, 1256 insertions, 0 deletions

diff --git a/src/cmd/internal/obj/link.go b/src/cmd/internal/obj/link.go
index 66748b25d2..17f1181c5e 100644
--- a/src/cmd/internal/obj/link.go
+++ b/src/cmd/internal/obj/link.go
@@ -369,6 +369,7 @@ const (
 	ABasePPC64
 	ABaseARM64
 	ABaseMIPS
+	ABaseRISCV
 	ABaseS390X
 	ABaseWasm
 
diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go
new file mode 100644
index 0000000000..81b429eb62
--- /dev/null
+++ b/src/cmd/internal/obj/riscv/anames.go
@@ -0,0 +1,244 @@
+// Code generated by stringer -i cpu.go -o anames.go -p riscv; DO NOT EDIT.
+
+package riscv
+
+import "cmd/internal/obj"
+
+var Anames = []string{
+	obj.A_ARCHSPECIFIC: "SLLIRV32",
+	"SRLIRV32",
+	"SRAIRV32",
+	"JAL",
+	"JALR",
+	"BEQ",
+	"BNE",
+	"BLT",
+	"BLTU",
+	"BGE",
+	"BGEU",
+	"FENCE",
+	"FENCEI",
+	"FENCETSO",
+	"ADDI",
+	"SLTI",
+	"SLTIU",
+	"ANDI",
+	"ORI",
+	"XORI",
+	"SLLI",
+	"SRLI",
+	"SRAI",
+	"LUI",
+	"AUIPC",
+	"ADD",
+	"SLT",
+	"SLTU",
+	"AND",
+	"OR",
+	"XOR",
+	"SLL",
+	"SRL",
+	"SUB",
+	"SRA",
+	"ADDIW",
+	"SLLIW",
+	"SRLIW",
+	"SRAIW",
+	"ADDW",
+	"SLLW",
+	"SRLW",
+	"SUBW",
+	"SRAW",
+	"LD",
+	"LW",
+	"LWU",
+	"LH",
+	"LHU",
+	"LB",
+	"LBU",
+	"SD",
+	"SW",
+	"SH",
+	"SB",
+	"RDCYCLE",
+	"RDCYCLEH",
+	"RDTIME",
+	"RDTIMEH",
+	"RDINSTRET",
+	"RDINSTRETH",
+	"MUL",
+	"MULH",
+	"MULHU",
+	"MULHSU",
+	"MULW",
+	"DIV",
+	"DIVU",
+	"REM",
+	"REMU",
+	"DIVW",
+	"DIVUW",
+	"REMW",
+	"REMUW",
+	"LRD",
+	"SCD",
+	"LRW",
+	"SCW",
+	"AMOSWAPD",
+	"AMOADDD",
+	"AMOANDD",
+	"AMOORD",
+	"AMOXORD",
+	"AMOMAXD",
+	"AMOMAXUD",
+	"AMOMIND",
+	"AMOMINUD",
+	"AMOSWAPW",
+	"AMOADDW",
+	"AMOANDW",
+	"AMOORW",
+	"AMOXORW",
+	"AMOMAXW",
+	"AMOMAXUW",
+	"AMOMINW",
+	"AMOMINUW",
+	"FRCSR",
+	"FSCSR",
+	"FRRM",
+	"FSRM",
+	"FRFLAGS",
+	"FSFLAGS",
+	"FSRMI",
+	"FSFLAGSI",
+	"FLW",
+	"FSW",
+	"FADDS",
+	"FSUBS",
+	"FMULS",
+	"FDIVS",
+	"FMINS",
+	"FMAXS",
+	"FSQRTS",
+	"FMADDS",
+	"FMSUBS",
+	"FNMADDS",
+	"FNMSUBS",
+	"FCVTWS",
+	"FCVTLS",
+	"FCVTSW",
+	"FCVTSL",
+	"FCVTWUS",
+	"FCVTLUS",
+	"FCVTSWU",
+	"FCVTSLU",
+	"FSGNJS",
+	"FSGNJNS",
+	"FSGNJXS",
+	"FMVSX",
+	"FMVXS",
+	"FMVWX",
+	"FMVXW",
+	"FEQS",
+	"FLTS",
+	"FLES",
+	"FCLASSS",
+	"FLD",
+	"FSD",
+	"FADDD",
+	"FSUBD",
+	"FMULD",
+	"FDIVD",
+	"FMIND",
+	"FMAXD",
+	"FSQRTD",
+	"FMADDD",
+	"FMSUBD",
+	"FNMADDD",
+	"FNMSUBD",
+	"FCVTWD",
+	"FCVTLD",
+	"FCVTDW",
+	"FCVTDL",
+	"FCVTWUD",
+	"FCVTLUD",
+	"FCVTDWU",
+	"FCVTDLU",
+	"FCVTSD",
+	"FCVTDS",
+	"FSGNJD",
+	"FSGNJND",
+	"FSGNJXD",
+	"FMVXD",
+	"FMVDX",
+	"FEQD",
+	"FLTD",
+	"FLED",
+	"FCLASSD",
+	"FLQ",
+	"FSQ",
+	"FADDQ",
+	"FSUBQ",
+	"FMULQ",
+	"FDIVQ",
+	"FMINQ",
+	"FMAXQ",
+	"FSQRTQ",
+	"FMADDQ",
+	"FMSUBQ",
+	"FNMADDQ",
+	"FNMSUBQ",
+	"FCVTWQ",
+	"FCVTLQ",
+	"FCVTSQ",
+	"FCVTDQ",
+	"FCVTQW",
+	"FCVTQL",
+	"FCVTQS",
+	"FCVTQD",
+	"FCVTWUQ",
+	"FCVTLUQ",
+	"FCVTQWU",
+	"FCVTQLU",
+	"FSGNJQ",
+	"FSGNJNQ",
+	"FSGNJXQ",
+	"FMVXQ",
+	"FMVQX",
+	"FEQQ",
+	"FLEQ",
+	"FLTQ",
+	"FCLASSQ",
+	"CSRRW",
+	"CSRRS",
+	"CSRRC",
+	"CSRRWI",
+	"CSRRSI",
+	"CSRRCI",
+	"ECALL",
+	"SCALL",
+	"EBREAK",
+	"SBREAK",
+	"MRET",
+	"SRET",
+	"URET",
+	"DRET",
+	"WFI",
+	"SFENCEVMA",
+	"HFENCEGVMA",
+	"HFENCEVVMA",
+	"WORD",
+	"FNEGD",
+	"FNEGS",
+	"FNED",
+	"FNES",
+	"MOV",
+	"MOVB",
+	"MOVBU",
+	"MOVF",
+	"MOVD",
+	"MOVH",
+	"MOVHU",
+	"MOVW",
+	"MOVWU",
+	"SEQZ",
+	"SNEZ",
+}
diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go
new file mode 100644
index 0000000000..30c7eb15ee
--- /dev/null
+++ b/src/cmd/internal/obj/riscv/cpu.go
@@ -0,0 +1,551 @@
+//	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
+//	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
+//	Portions Copyright © 1997-1999 Vita Nuova Limited
+//	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
+//	Portions Copyright © 2004,2006 Bruce Ellis
+//	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
+//	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
+//	Portions Copyright © 2009 The Go Authors.  All rights reserved.
+//	Portions Copyright © 2019 The Go Authors.  All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+
+package riscv
+
+import "cmd/internal/obj"
+
+//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
+
+const (
+	// Base register numberings.
+	REG_X0 = obj.RBaseRISCV + iota
+	REG_X1
+	REG_X2
+	REG_X3
+	REG_X4
+	REG_X5
+	REG_X6
+	REG_X7
+	REG_X8
+	REG_X9
+	REG_X10
+	REG_X11
+	REG_X12
+	REG_X13
+	REG_X14
+	REG_X15
+	REG_X16
+	REG_X17
+	REG_X18
+	REG_X19
+	REG_X20
+	REG_X21
+	REG_X22
+	REG_X23
+	REG_X24
+	REG_X25
+	REG_X26
+	REG_X27
+	REG_X28
+	REG_X29
+	REG_X30
+	REG_X31
+
+	// FP register numberings.
+	REG_F0
+	REG_F1
+	REG_F2
+	REG_F3
+	REG_F4
+	REG_F5
+	REG_F6
+	REG_F7
+	REG_F8
+	REG_F9
+	REG_F10
+	REG_F11
+	REG_F12
+	REG_F13
+	REG_F14
+	REG_F15
+	REG_F16
+	REG_F17
+	REG_F18
+	REG_F19
+	REG_F20
+	REG_F21
+	REG_F22
+	REG_F23
+	REG_F24
+	REG_F25
+	REG_F26
+	REG_F27
+	REG_F28
+	REG_F29
+	REG_F30
+	REG_F31
+
+	// This marks the end of the register numbering.
+	REG_END
+
+	// General registers reassigned to ABI names.
+	REG_ZERO = REG_X0
+	REG_RA   = REG_X1
+	REG_SP   = REG_X2
+	REG_GP   = REG_X3 // aka REG_SB
+	REG_TP   = REG_X4 // aka REG_G
+	REG_T0   = REG_X5
+	REG_T1   = REG_X6
+	REG_T2   = REG_X7
+	REG_S0   = REG_X8
+	REG_S1   = REG_X9
+	REG_A0   = REG_X10
+	REG_A1   = REG_X11
+	REG_A2   = REG_X12
+	REG_A3   = REG_X13
+	REG_A4   = REG_X14
+	REG_A5   = REG_X15
+	REG_A6   = REG_X16
+	REG_A7   = REG_X17
+	REG_S2   = REG_X18
+	REG_S3   = REG_X19
+	REG_S4   = REG_X20
+	REG_S5   = REG_X21
+	REG_S6   = REG_X22
+	REG_S7   = REG_X23
+	REG_S8   = REG_X24
+	REG_S9   = REG_X25
+	REG_S10  = REG_X26
+	REG_S11  = REG_X27
+	REG_T3   = REG_X28
+	REG_T4   = REG_X29
+	REG_T5   = REG_X30
+	REG_T6   = REG_X31
+
+	// Go runtime register names.
+	REG_G    = REG_TP // G pointer.
+	REG_CTXT = REG_S4 // Context for closures.
+	REG_TMP  = REG_T6 // Reserved for assembler use.
+
+	// ABI names for floating point registers.
+	REG_FT0  = REG_F0
+	REG_FT1  = REG_F1
+	REG_FT2  = REG_F2
+	REG_FT3  = REG_F3
+	REG_FT4  = REG_F4
+	REG_FT5  = REG_F5
+	REG_FT6  = REG_F6
+	REG_FT7  = REG_F7
+	REG_FS0  = REG_F8
+	REG_FS1  = REG_F9
+	REG_FA0  = REG_F10
+	REG_FA1  = REG_F11
+	REG_FA2  = REG_F12
+	REG_FA3  = REG_F13
+	REG_FA4  = REG_F14
+	REG_FA5  = REG_F15
+	REG_FA6  = REG_F16
+	REG_FA7  = REG_F17
+	REG_FS2  = REG_F18
+	REG_FS3  = REG_F19
+	REG_FS4  = REG_F20
+	REG_FS5  = REG_F21
+	REG_FS6  = REG_F22
+	REG_FS7  = REG_F23
+	REG_FS8  = REG_F24
+	REG_FS9  = REG_F25
+	REG_FS10 = REG_F26
+	REG_FS11 = REG_F27
+	REG_FT8  = REG_F28
+	REG_FT9  = REG_F29
+	REG_FT10 = REG_F30
+	REG_FT11 = REG_F31
+
+	// Names generated by the SSA compiler.
+	REGSP = REG_SP
+	REGG  = REG_G
+)
+
+// Prog.Mark flags.
+const (
+	// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
+	// it is the first instruction in an AUIPC + I-type pair that needs a
+	// R_RISCV_PCREL_ITYPE relocation.
+	NEED_PCREL_ITYPE_RELOC = 1 << 0
+
+	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
+	// it is the first instruction in an AUIPC + S-type pair that needs a
+	// R_RISCV_PCREL_STYPE relocation.
+	NEED_PCREL_STYPE_RELOC = 1 << 1
+)
+
+// RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
+// from:
+//
+//    https://github.com/riscv/riscv-opcodes
+//
+// As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
+//
+// See also "The RISC-V Instruction Set Manual" at:
+//
+//    https://riscv.org/specifications/
+//
+// If you modify this table, you MUST run 'go generate' to regenerate anames.go!
+const (
+	// Unprivileged ISA (Document Version 20190608-Base-Ratified)
+
+	// 2.4: Integer Computational Instructions
+	ASLLIRV32 = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
+	ASRLIRV32
+	ASRAIRV32
+
+	// 2.5: Control Transfer Instructions
+	AJAL
+	AJALR
+	ABEQ
+	ABNE
+	ABLT
+	ABLTU
+	ABGE
+	ABGEU
+
+	// 2.7: Memory Ordering Instructions
+	AFENCE
+	AFENCEI
+	AFENCETSO
+
+	// 5.2: Integer Computational Instructions
+	AADDI
+	ASLTI
+	ASLTIU
+	AANDI
+	AORI
+	AXORI
+	ASLLI
+	ASRLI
+	ASRAI
+	ALUI
+	AAUIPC
+	AADD
+	ASLT
+	ASLTU
+	AAND
+	AOR
+	AXOR
+	ASLL
+	ASRL
+	ASUB
+	ASRA
+	AADDIW
+	ASLLIW
+	ASRLIW
+	ASRAIW
+	AADDW
+	ASLLW
+	ASRLW
+	ASUBW
+	ASRAW
+
+	// 5.3: Load and Store Instructions
+	ALD
+	ALW
+	ALWU
+	ALH
+	ALHU
+	ALB
+	ALBU
+	ASD
+	ASW
+	ASH
+	ASB
+
+	// 7.1: Multiplication Operations
+	AMUL
+	AMULH
+	AMULHU
+	AMULHSU
+	AMULW
+	ADIV
+	ADIVU
+	AREM
+	AREMU
+	ADIVW
+	ADIVUW
+	AREMW
+	AREMUW
+
+	// 8.2: Load-Reserved/Store-Conditional Instructions
+	ALRD
+	ASCD
+	ALRW
+	ASCW
+
+	// 8.3: Atomic Memory Operations
+	AAMOSWAPD
+	AAMOADDD
+	AAMOANDD
+	AAMOORD
+	AAMOXORD
+	AAMOMAXD
+	AAMOMAXUD
+	AAMOMIND
+	AAMOMINUD
+	AAMOSWAPW
+	AAMOADDW
+	AAMOANDW
+	AAMOORW
+	AAMOXORW
+	AAMOMAXW
+	AAMOMAXUW
+	AAMOMINW
+	AAMOMINUW
+
+	// 10.1: Base Counters and Timers
+	ARDCYCLE
+	ARDCYCLEH
+	ARDTIME
+	ARDTIMEH
+	ARDINSTRET
+	ARDINSTRETH
+
+	// 11.2: Floating-Point Control and Status Register
+	AFRCSR
+	AFSCSR
+	AFRRM
+	AFSRM
+	AFRFLAGS
+	AFSFLAGS
+	AFSRMI
+	AFSFLAGSI
+
+	// 11.5: Single-Precision Load and Store Instructions
+	AFLW
+	AFSW
+
+	// 11.6: Single-Precision Floating-Point Computational Instructions
+	AFADDS
+	AFSUBS
+	AFMULS
+	AFDIVS
+	AFMINS
+	AFMAXS
+	AFSQRTS
+	AFMADDS
+	AFMSUBS
+	AFNMADDS
+	AFNMSUBS
+
+	// 11.7: Single-Precision Floating-Point Conversion and Move Instructions
+	AFCVTWS
+	AFCVTLS
+	AFCVTSW
+	AFCVTSL
+	AFCVTWUS
+	AFCVTLUS
+	AFCVTSWU
+	AFCVTSLU
+	AFSGNJS
+	AFSGNJNS
+	AFSGNJXS
+	AFMVSX
+	AFMVXS
+	AFMVWX
+	AFMVXW
+
+	// 11.8: Single-Precision Floating-Point Compare Instructions
+	AFEQS
+	AFLTS
+	AFLES
+
+	// 11.9: Single-Precision Floating-Point Classify Instruction
+	AFCLASSS
+
+	// 12.3: Double-Precision Load and Store Instructions
+	AFLD
+	AFSD
+
+	// 12.4: Double-Precision Floating-Point Computational Instructions
+	AFADDD
+	AFSUBD
+	AFMULD
+	AFDIVD
+	AFMIND
+	AFMAXD
+	AFSQRTD
+	AFMADDD
+	AFMSUBD
+	AFNMADDD
+	AFNMSUBD
+
+	// 12.5: Double-Precision Floating-Point Conversion and Move Instructions
+	AFCVTWD
+	AFCVTLD
+	AFCVTDW
+	AFCVTDL
+	AFCVTWUD
+	AFCVTLUD
+	AFCVTDWU
+	AFCVTDLU
+	AFCVTSD
+	AFCVTDS
+	AFSGNJD
+	AFSGNJND
+	AFSGNJXD
+	AFMVXD
+	AFMVDX
+
+	// 12.6: Double-Precision Floating-Point Compare Instructions
+	AFEQD
+	AFLTD
+	AFLED
+
+	// 12.7: Double-Precision Floating-Point Classify Instruction
+	AFCLASSD
+
+	// 13.1 Quad-Precision Load and Store Instructions
+	AFLQ
+	AFSQ
+
+	// 13.2: Quad-Precision Computational Instructions
+	AFADDQ
+	AFSUBQ
+	AFMULQ
+	AFDIVQ
+	AFMINQ
+	AFMAXQ
+	AFSQRTQ
+	AFMADDQ
+	AFMSUBQ
+	AFNMADDQ
+	AFNMSUBQ
+
+	// 13.3 Quad-Precision Convert and Move Instructions
+	AFCVTWQ
+	AFCVTLQ
+	AFCVTSQ
+	AFCVTDQ
+	AFCVTQW
+	AFCVTQL
+	AFCVTQS
+	AFCVTQD
+	AFCVTWUQ
+	AFCVTLUQ
+	AFCVTQWU
+	AFCVTQLU
+	AFSGNJQ
+	AFSGNJNQ
+	AFSGNJXQ
+	AFMVXQ
+	AFMVQX
+
+	// 13.4 Quad-Precision Floating-Point Compare Instructions
+	AFEQQ
+	AFLEQ
+	AFLTQ
+
+	// 13.5 Quad-Precision Floating-Point Classify Instruction
+	AFCLASSQ
+
+	// Privileged ISA (Version 20190608-Priv-MSU-Ratified)
+
+	// 3.1.9: Instructions to Access CSRs
+	ACSRRW
+	ACSRRS
+	ACSRRC
+	ACSRRWI
+	ACSRRSI
+	ACSRRCI
+
+	// 3.2.1: Environment Call and Breakpoint
+	AECALL
+	ASCALL
+	AEBREAK
+	ASBREAK
+
+	// 3.2.2: Trap-Return Instructions
+	AMRET
+	ASRET
+	AURET
+	ADRET
+
+	// 3.2.3: Wait for Interrupt
+	AWFI
+
+	// 4.2.1: Supervisor Memory-Management Fence Instruction
+	ASFENCEVMA
+
+	// Hypervisor Memory-Management Instructions
+	AHFENCEGVMA
+	AHFENCEVVMA
+
+	// The escape hatch. Inserts a single 32-bit word.
+	AWORD
+
+	// Pseudo-instructions.  These get translated by the assembler into other
+	// instructions, based on their operands.
+	AFNEGD
+	AFNEGS
+	AFNED
+	AFNES
+	AMOV
+	AMOVB
+	AMOVBU
+	AMOVF
+	AMOVD
+	AMOVH
+	AMOVHU
+	AMOVW
+	AMOVWU
+	ASEQZ
+	ASNEZ
+)
+
+// All unary instructions which write to their arguments (as opposed to reading
+// from them) go here. The assembly parser uses this information to populate
+// its AST in a semantically reasonable way.
+//
+// Any instructions not listed here are assumed to either be non-unary or to read
+// from its argument.
+var unaryDst = map[obj.As]bool{
+	ARDCYCLE:    true,
+	ARDCYCLEH:   true,
+	ARDTIME:     true,
+	ARDTIMEH:    true,
+	ARDINSTRET:  true,
+	ARDINSTRETH: true,
+}
+
+// Instruction encoding masks.
+const (
+	// ITypeImmMask is a mask including only the immediate portion of
+	// I-type instructions.
+	ITypeImmMask = 0xfff00000
+
+	// STypeImmMask is a mask including only the immediate portion of
+	// S-type instructions.
+	STypeImmMask = 0xfe000f80
+
+	// UTypeImmMask is a mask including only the immediate portion of
+	// U-type instructions.
+	UTypeImmMask = 0xfffff000
+
+	// UJTypeImmMask is a mask including only the immediate portion of
+	// UJ-type instructions.
+	UJTypeImmMask = UTypeImmMask
+)
diff --git a/src/cmd/internal/obj/riscv/inst.go b/src/cmd/internal/obj/riscv/inst.go
new file mode 100644
index 0000000000..891199e0e0
--- /dev/null
+++ b/src/cmd/internal/obj/riscv/inst.go
@@ -0,0 +1,459 @@
+// Code generated by parse_opcodes -go; DO NOT EDIT.
+
+package riscv
+
+import "cmd/internal/obj"
+
+type inst struct {
+	opcode uint32
+	funct3 uint32
+	rs2    uint32
+	csr    int64
+	funct7 uint32
+}
+
+func encode(a obj.As) *inst {
+	switch a {
+	case ABEQ:
+		return &inst{0x63, 0x0, 0x0, 0, 0x0}
+	case ABNE:
+		return &inst{0x63, 0x1, 0x0, 0, 0x0}
+	case ABLT:
+		return &inst{0x63, 0x4, 0x0, 0, 0x0}
+	case ABGE:
+		return &inst{0x63, 0x5, 0x0, 0, 0x0}
+	case ABLTU:
+		return &inst{0x63, 0x6, 0x0, 0, 0x0}
+	case ABGEU:
+		return &inst{0x63, 0x7, 0x0, 0, 0x0}
+	case AJALR:
+		return &inst{0x67, 0x0, 0x0, 0, 0x0}
+	case AJAL:
+		return &inst{0x6f, 0x0, 0x0, 0, 0x0}
+	case ALUI:
+		return &inst{0x37, 0x0, 0x0, 0, 0x0}
+	case AAUIPC:
+		return &inst{0x17, 0x0, 0x0, 0, 0x0}
+	case AADDI:
+		return &inst{0x13, 0x0, 0x0, 0, 0x0}
+	case ASLLI:
+		return &inst{0x13, 0x1, 0x0, 0, 0x0}
+	case ASLTI:
+		return &inst{0x13, 0x2, 0x0, 0, 0x0}
+	case ASLTIU:
+		return &inst{0x13, 0x3, 0x0, 0, 0x0}
+	case AXORI:
+		return &inst{0x13, 0x4, 0x0, 0, 0x0}
+	case ASRLI:
+		return &inst{0x13, 0x5, 0x0, 0, 0x0}
+	case ASRAI:
+		return &inst{0x13, 0x5, 0x0, 1024, 0x20}
+	case AORI:
+		return &inst{0x13, 0x6, 0x0, 0, 0x0}
+	case AANDI:
+		return &inst{0x13, 0x7, 0x0, 0, 0x0}
+	case AADD:
+		return &inst{0x33, 0x0, 0x0, 0, 0x0}
+	case ASUB:
+		return &inst{0x33, 0x0, 0x0, 1024, 0x20}
+	case ASLL:
+		return &inst{0x33, 0x1, 0x0, 0, 0x0}
+	case ASLT:
+		return &inst{0x33, 0x2, 0x0, 0, 0x0}
+	case ASLTU:
+		return &inst{0x33, 0x3, 0x0, 0, 0x0}
+	case AXOR:
+		return &inst{0x33, 0x4, 0x0, 0, 0x0}
+	case ASRL:
+		return &inst{0x33, 0x5, 0x0, 0, 0x0}
+	case ASRA:
+		return &inst{0x33, 0x5, 0x0, 1024, 0x20}
+	case AOR:
+		return &inst{0x33, 0x6, 0x0, 0, 0x0}
+	case AAND:
+		return &inst{0x33, 0x7, 0x0, 0, 0x0}
+	case AADDIW:
+		return &inst{0x1b, 0x0, 0x0, 0, 0x0}
+	case ASLLIW:
+		return &inst{0x1b, 0x1, 0x0, 0, 0x0}
+	case ASRLIW:
+		return &inst{0x1b, 0x5, 0x0, 0, 0x0}
+	case ASRAIW:
+		return &inst{0x1b, 0x5, 0x0, 1024, 0x20}
+	case AADDW:
+		return &inst{0x3b, 0x0, 0x0, 0, 0x0}
+	case ASUBW:
+		return &inst{0x3b, 0x0, 0x0, 1024, 0x20}
+	case ASLLW:
+		return &inst{0x3b, 0x1, 0x0, 0, 0x0}
+	case ASRLW:
+		return &inst{0x3b, 0x5, 0x0, 0, 0x0}
+	case ASRAW:
+		return &inst{0x3b, 0x5, 0x0, 1024, 0x20}
+	case ALB:
+		return &inst{0x3, 0x0, 0x0, 0, 0x0}
+	case ALH:
+		return &inst{0x3, 0x1, 0x0, 0, 0x0}
+	case ALW:
+		return &inst{0x3, 0x2, 0x0, 0, 0x0}
+	case ALD:
+		return &inst{0x3, 0x3, 0x0, 0, 0x0}
+	case ALBU:
+		return &inst{0x3, 0x4, 0x0, 0, 0x0}
+	case ALHU:
+		return &inst{0x3, 0x5, 0x0, 0, 0x0}
+	case ALWU:
+		return &inst{0x3, 0x6, 0x0, 0, 0x0}
+	case ASB:
+		return &inst{0x23, 0x0, 0x0, 0, 0x0}
+	case ASH:
+		return &inst{0x23, 0x1, 0x0, 0, 0x0}
+	case ASW:
+		return &inst{0x23, 0x2, 0x0, 0, 0x0}
+	case ASD:
+		return &inst{0x23, 0x3, 0x0, 0, 0x0}
+	case AFENCE:
+		return &inst{0xf, 0x0, 0x0, 0, 0x0}
+	case AFENCEI:
+		return &inst{0xf, 0x1, 0x0, 0, 0x0}
+	case AMUL:
+		return &inst{0x33, 0x0, 0x0, 32, 0x1}
+	case AMULH:
+		return &inst{0x33, 0x1, 0x0, 32, 0x1}
+	case AMULHSU:
+		return &inst{0x33, 0x2, 0x0, 32, 0x1}
+	case AMULHU:
+		return &inst{0x33, 0x3, 0x0, 32, 0x1}
+	case ADIV:
+		return &inst{0x33, 0x4, 0x0, 32, 0x1}
+	case ADIVU:
+		return &inst{0x33, 0x5, 0x0, 32, 0x1}
+	case AREM:
+		return &inst{0x33, 0x6, 0x0, 32, 0x1}
+	case AREMU:
+		return &inst{0x33, 0x7, 0x0, 32, 0x1}
+	case AMULW:
+		return &inst{0x3b, 0x0, 0x0, 32, 0x1}
+	case ADIVW:
+		return &inst{0x3b, 0x4, 0x0, 32, 0x1}
+	case ADIVUW:
+		return &inst{0x3b, 0x5, 0x0, 32, 0x1}
+	case AREMW:
+		return &inst{0x3b, 0x6, 0x0, 32, 0x1}
+	case AREMUW:
+		return &inst{0x3b, 0x7, 0x0, 32, 0x1}
+	case AAMOADDW:
+		return &inst{0x2f, 0x2, 0x0, 0, 0x0}
+	case AAMOXORW:
+		return &inst{0x2f, 0x2, 0x0, 512, 0x10}
+	case AAMOORW:
+		return &inst{0x2f, 0x2, 0x0, 1024, 0x20}
+	case AAMOANDW:
+		return &inst{0x2f, 0x2, 0x0, 1536, 0x30}
+	case AAMOMINW:
+		return &inst{0x2f, 0x2, 0x0, -2048, 0x40}
+	case AAMOMAXW:
+		return &inst{0x2f, 0x2, 0x0, -1536, 0x50}
+	case AAMOMINUW:
+		return &inst{0x2f, 0x2, 0x0, -1024, 0x60}
+	case AAMOMAXUW:
+		return &inst{0x2f, 0x2, 0x0, -512, 0x70}
+	case AAMOSWAPW:
+		return &inst{0x2f, 0x2, 0x0, 128, 0x4}
+	case ALRW:
+		return &inst{0x2f, 0x2, 0x0, 256, 0x8}
+	case ASCW:
+		return &inst{0x2f, 0x2, 0x0, 384, 0xc}
+	case AAMOADDD:
+		return &inst{0x2f, 0x3, 0x0, 0, 0x0}
+	case AAMOXORD:
+		return &inst{0x2f, 0x3, 0x0, 512, 0x10}
+	case AAMOORD:
+		return &inst{0x2f, 0x3, 0x0, 1024, 0x20}
+	case AAMOANDD:
+		return &inst{0x2f, 0x3, 0x0, 1536, 0x30}
+	case AAMOMIND:
+		return &inst{0x2f, 0x3, 0x0, -2048, 0x40}
+	case AAMOMAXD:
+		return &inst{0x2f, 0x3, 0x0, -1536, 0x50}
+	case AAMOMINUD:
+		return &inst{0x2f, 0x3, 0x0, -1024, 0x60}
+	case AAMOMAXUD:
+		return &inst{0x2f, 0x3, 0x0, -512, 0x70}
+	case AAMOSWAPD:
+		return &inst{0x2f, 0x3, 0x0, 128, 0x4}
+	case ALRD:
+		return &inst{0x2f, 0x3, 0x0, 256, 0x8}
+	case ASCD:
+		return &inst{0x2f, 0x3, 0x0, 384, 0xc}
+	case AECALL:
+		return &inst{0x73, 0x0, 0x0, 0, 0x0}
+	case AEBREAK:
+		return &inst{0x73, 0x0, 0x1, 1, 0x0}
+	case AURET:
+		return &inst{0x73, 0x0, 0x2, 2, 0x0}
+	case ASRET:
+		return &inst{0x73, 0x0, 0x2, 258, 0x8}
+	case AMRET:
+		return &inst{0x73, 0x0, 0x2, 770, 0x18}
+	case ADRET:
+		return &inst{0x73, 0x0, 0x12, 1970, 0x3d}
+	case ASFENCEVMA:
+		return &inst{0x73, 0x0, 0x0, 288, 0x9}
+	case AWFI:
+		return &inst{0x73, 0x0, 0x5, 261, 0x8}
+	case ACSRRW:
+		return &inst{0x73, 0x1, 0x0, 0, 0x0}
+	case ACSRRS:
+		return &inst{0x73, 0x2, 0x0, 0, 0x0}
+	case ACSRRC:
+		return &inst{0x73, 0x3, 0x0, 0, 0x0}
+	case ACSRRWI:
+		return &inst{0x73, 0x5, 0x0, 0, 0x0}
+	case ACSRRSI:
+		return &inst{0x73, 0x6, 0x0, 0, 0x0}
+	case ACSRRCI:
+		return &inst{0x73, 0x7, 0x0, 0, 0x0}
+	case AHFENCEVVMA:
+		return &inst{0x73, 0x0, 0x0, 544, 0x11}
+	case AHFENCEGVMA:
+		return &inst{0x73, 0x0, 0x0, 1568, 0x31}
+	case AFADDS:
+		return &inst{0x53, 0x0, 0x0, 0, 0x0}
+	case AFSUBS:
+		return &inst{0x53, 0x0, 0x0, 128, 0x4}
+	case AFMULS:
+		return &inst{0x53, 0x0, 0x0, 256, 0x8}
+	case AFDIVS:
+		return &inst{0x53, 0x0, 0x0, 384, 0xc}
+	case AFSGNJS:
+		return &inst{0x53, 0x0, 0x0, 512, 0x10}
+	case AFSGNJNS:
+		return &inst{0x53, 0x1, 0x0, 512, 0x10}
+	case AFSGNJXS:
+		return &inst{0x53, 0x2, 0x0, 512, 0x10}
+	case AFMINS:
+		return &inst{0x53, 0x0, 0x0, 640, 0x14}
+	case AFMAXS:
+		return &inst{0x53, 0x1, 0x0, 640, 0x14}
+	case AFSQRTS:
+		return &inst{0x53, 0x0, 0x0, 1408, 0x2c}
+	case AFADDD:
+		return &inst{0x53, 0x0, 0x0, 32, 0x1}
+	case AFSUBD:
+		return &inst{0x53, 0x0, 0x0, 160, 0x5}
+	case AFMULD:
+		return &inst{0x53, 0x0, 0x0, 288, 0x9}
+	case AFDIVD:
+		return &inst{0x53, 0x0, 0x0, 416, 0xd}
+	case AFSGNJD:
+		return &inst{0x53, 0x0, 0x0, 544, 0x11}
+	case AFSGNJND:
+		return &inst{0x53, 0x1, 0x0, 544, 0x11}
+	case AFSGNJXD:
+		return &inst{0x53, 0x2, 0x0, 544, 0x11}
+	case AFMIND:
+		return &inst{0x53, 0x0, 0x0, 672, 0x15}
+	case AFMAXD:
+		return &inst{0x53, 0x1, 0x0, 672, 0x15}
+	case AFCVTSD:
+		return &inst{0x53, 0x0, 0x1, 1025, 0x20}
+	case AFCVTDS:
+		return &inst{0x53, 0x0, 0x0, 1056, 0x21}
+	case AFSQRTD:
+		return &inst{0x53, 0x0, 0x0, 1440, 0x2d}
+	case AFADDQ:
+		return &inst{0x53, 0x0, 0x0, 96, 0x3}
+	case AFSUBQ:
+		return &inst{0x53, 0x0, 0x0, 224, 0x7}
+	case AFMULQ:
+		return &inst{0x53, 0x0, 0x0, 352, 0xb}
+	case AFDIVQ:
+		return &inst{0x53, 0x0, 0x0, 480, 0xf}
+	case AFSGNJQ:
+		return &inst{0x53, 0x0, 0x0, 608, 0x13}
+	case AFSGNJNQ:
+		return &inst{0x53, 0x1, 0x0, 608, 0x13}
+	case AFSGNJXQ:
+		return &inst{0x53, 0x2, 0x0, 608, 0x13}
+	case AFMINQ:
+		return &inst{0x53, 0x0, 0x0, 736, 0x17}
+	case AFMAXQ:
+		return &inst{0x53, 0x1, 0x0, 736, 0x17}
+	case AFCVTSQ:
+		return &inst{0x53, 0x0, 0x3, 1027, 0x20}
+	case AFCVTQS:
+		return &inst{0x53, 0x0, 0x0, 1120, 0x23}
+	case AFCVTDQ:
+		return &inst{0x53, 0x0, 0x3, 1059, 0x21}
+	case AFCVTQD:
+		return &inst{0x53, 0x0, 0x1, 1121, 0x23}
+	case AFSQRTQ:
+		return &inst{0x53, 0x0, 0x0, 1504, 0x2f}
+	case AFLES:
+		return &inst{0x53, 0x0, 0x0, -1536, 0x50}
+	case AFLTS:
+		return &inst{0x53, 0x1, 0x0, -1536, 0x50}
+	case AFEQS:
+		return &inst{0x53, 0x2, 0x0, -1536, 0x50}
+	case AFLED:
+		return &inst{0x53, 0x0, 0x0, -1504, 0x51}
+	case AFLTD:
+		return &inst{0x53, 0x1, 0x0, -1504, 0x51}
+	case AFEQD:
+		return &inst{0x53, 0x2, 0x0, -1504, 0x51}
+	case AFLEQ:
+		return &inst{0x53, 0x0, 0x0, -1440, 0x53}
+	case AFLTQ:
+		return &inst{0x53, 0x1, 0x0, -1440, 0x53}
+	case AFEQQ:
+		return &inst{0x53, 0x2, 0x0, -1440, 0x53}
+	case AFCVTWS:
+		return &inst{0x53, 0x0, 0x0, -1024, 0x60}
+	case AFCVTWUS:
+		return &inst{0x53, 0x0, 0x1, -1023, 0x60}
+	case AFCVTLS:
+		return &inst{0x53, 0x0, 0x2, -1022, 0x60}
+	case AFCVTLUS:
+		return &inst{0x53, 0x0, 0x3, -1021, 0x60}
+	case AFMVXW:
+		return &inst{0x53, 0x0, 0x0, -512, 0x70}
+	case AFCLASSS:
+		return &inst{0x53, 0x1, 0x0, -512, 0x70}
+	case AFCVTWD:
+		return &inst{0x53, 0x0, 0x0, -992, 0x61}
+	case AFCVTWUD:
+		return &inst{0x53, 0x0, 0x1, -991, 0x61}
+	case AFCVTLD:
+		return &inst{0x53, 0x0, 0x2, -990, 0x61}
+	case AFCVTLUD:
+		return &inst{0x53, 0x0, 0x3, -989, 0x61}
+	case AFMVXD:
+		return &inst{0x53, 0x0, 0x0, -480, 0x71}
+	case AFCLASSD:
+		return &inst{0x53, 0x1, 0x0, -480, 0x71}
+	case AFCVTWQ:
+		return &inst{0x53, 0x0, 0x0, -928, 0x63}
+	case AFCVTWUQ:
+		return &inst{0x53, 0x0, 0x1, -927, 0x63}
+	case AFCVTLQ:
+		return &inst{0x53, 0x0, 0x2, -926, 0x63}
+	case AFCVTLUQ:
+		return &inst{0x53, 0x0, 0x3, -925, 0x63}
+	case AFMVXQ:
+		return &inst{0x53, 0x0, 0x0, -416, 0x73}
+	case AFCLASSQ:
+		return &inst{0x53, 0x1, 0x0, -416, 0x73}
+	case AFCVTSW:
+		return &inst{0x53, 0x0, 0x0, -768, 0x68}
+	case AFCVTSWU:
+		return &inst{0x53, 0x0, 0x1, -767, 0x68}
+	case AFCVTSL:
+		return &inst{0x53, 0x0, 0x2, -766, 0x68}
+	case AFCVTSLU:
+		return &inst{0x53, 0x0, 0x3, -765, 0x68}
+	case AFMVWX:
+		return &inst{0x53, 0x0, 0x0, -256, 0x78}
+	case AFCVTDW:
+		return &inst{0x53, 0x0, 0x0, -736, 0x69}
+	case AFCVTDWU:
+		return &inst{0x53, 0x0, 0x1, -735, 0x69}
+	case AFCVTDL:
+		return &inst{0x53, 0x0, 0x2, -734, 0x69}
+	case AFCVTDLU:
+		return &inst{0x53, 0x0, 0x3, -733, 0x69}
+	case AFMVDX:
+		return &inst{0x53, 0x0, 0x0, -224, 0x79}
+	case AFCVTQW:
+		return &inst{0x53, 0x0, 0x0, -672, 0x6b}
+	case AFCVTQWU:
+		return &inst{0x53, 0x0, 0x1, -671, 0x6b}
+	case AFCVTQL:
+		return &inst{0x53, 0x0, 0x2, -670, 0x6b}
+	case AFCVTQLU:
+		return &inst{0x53, 0x0, 0x3, -669, 0x6b}
+	case AFMVQX:
+		return &inst{0x53, 0x0, 0x0, -160, 0x7b}
+	case AFLW:
+		return &inst{0x7, 0x2, 0x0, 0, 0x0}
+	case AFLD:
+		return &inst{0x7, 0x3, 0x0, 0, 0x0}
+	case AFLQ:
+		return &inst{0x7, 0x4, 0x0, 0, 0x0}
+	case AFSW:
+		return &inst{0x27, 0x2, 0x0, 0, 0x0}
+	case AFSD:
+		return &inst{0x27, 0x3, 0x0, 0, 0x0}
+	case AFSQ:
+		return &inst{0x27, 0x4, 0x0, 0, 0x0}
+	case AFMADDS:
+		return &inst{0x43, 0x0, 0x0, 0, 0x0}
+	case AFMSUBS:
+		return &inst{0x47, 0x0, 0x0, 0, 0x0}
+	case AFNMSUBS:
+		return &inst{0x4b, 0x0, 0x0, 0, 0x0}
+	case AFNMADDS:
+		return &inst{0x4f, 0x0, 0x0, 0, 0x0}
+	case AFMADDD:
+		return &inst{0x43, 0x0, 0x0, 32, 0x1}
+	case AFMSUBD:
+		return &inst{0x47, 0x0, 0x0, 32, 0x1}
+	case AFNMSUBD:
+		return &inst{0x4b, 0x0, 0x0, 32, 0x1}
+	case AFNMADDD:
+		return &inst{0x4f, 0x0, 0x0, 32, 0x1}
+	case AFMADDQ:
+		return &inst{0x43, 0x0, 0x0, 96, 0x3}
+	case AFMSUBQ:
+		return &inst{0x47, 0x0, 0x0, 96, 0x3}
+	case AFNMSUBQ:
+		return &inst{0x4b, 0x0, 0x0, 96, 0x3}
+	case AFNMADDQ:
+		return &inst{0x4f, 0x0, 0x0, 96, 0x3}
+	case ASLLIRV32:
+		return &inst{0x13, 0x1, 0x0, 0, 0x0}
+	case ASRLIRV32:
+		return &inst{0x13, 0x5, 0x0, 0, 0x0}
+	case ASRAIRV32:
+		return &inst{0x13, 0x5, 0x0, 1024, 0x20}
+	case AFRFLAGS:
+		return &inst{0x73, 0x2, 0x1, 1, 0x0}
+	case AFSFLAGS:
+		return &inst{0x73, 0x1, 0x1, 1, 0x0}
+	case AFSFLAGSI:
+		return &inst{0x73, 0x5, 0x1, 1, 0x0}
+	case AFRRM:
+		return &inst{0x73, 0x2, 0x2, 2, 0x0}
+	case AFSRM:
+		return &inst{0x73, 0x1, 0x2, 2, 0x0}
+	case AFSRMI:
+		return &inst{0x73, 0x5, 0x2, 2, 0x0}
+	case AFSCSR:
+		return &inst{0x73, 0x1, 0x3, 3, 0x0}
+	case AFRCSR:
+		return &inst{0x73, 0x2, 0x3, 3, 0x0}
+	case ARDCYCLE:
+		return &inst{0x73, 0x2, 0x0, -1024, 0x60}
+	case ARDTIME:
+		return &inst{0x73, 0x2, 0x1, -1023, 0x60}
+	case ARDINSTRET:
+		return &inst{0x73, 0x2, 0x2, -1022, 0x60}
+	case ARDCYCLEH:
+		return &inst{0x73, 0x2, 0x0, -896, 0x64}
+	case ARDTIMEH:
+		return &inst{0x73, 0x2, 0x1, -895, 0x64}
+	case ARDINSTRETH:
+		return &inst{0x73, 0x2, 0x2, -894, 0x64}
+	case ASCALL:
+		return &inst{0x73, 0x0, 0x0, 0, 0x0}
+	case ASBREAK:
+		return &inst{0x73, 0x0, 0x1, 1, 0x0}
+	case AFMVXS:
+		return &inst{0x53, 0x0, 0x0, -512, 0x70}
+	case AFMVSX:
+		return &inst{0x53, 0x0, 0x0, -256, 0x78}
+	case AFENCETSO:
+		return &inst{0xf, 0x0, 0x13, -1997, 0x41}
+	}
+	return nil
+}
diff --git a/src/cmd/internal/obj/util.go b/src/cmd/internal/obj/util.go
index f1517d3d5d..46d662c6c8 100644
--- a/src/cmd/internal/obj/util.go
+++ b/src/cmd/internal/obj/util.go
@@ -457,6 +457,7 @@ const (
 	RBaseARM64 = 8 * 1024  // range [8k, 13k)
 	RBaseMIPS  = 13 * 1024 // range [13k, 14k)
 	RBaseS390X = 14 * 1024 // range [14k, 15k)
+	RBaseRISCV = 15 * 1024 // range [15k, 16k)
 	RBaseWasm  = 16 * 1024
 )